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https://github.com/RPCS3/llvm-mirror.git
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CodeGen: Remove more ilist iterator implicit conversions, NFC
llvm-svn: 249879
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e4bfe005a9
commit
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@ -462,11 +462,11 @@ bool IfConverter::ReverseBranchCondition(BBInfo &BBI) {
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/// getNextBlock - Returns the next block in the function blocks ordering. If
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/// it is the end, returns NULL.
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static inline MachineBasicBlock *getNextBlock(MachineBasicBlock *BB) {
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MachineFunction::iterator I = BB;
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MachineFunction::iterator I = BB->getIterator();
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MachineFunction::iterator E = BB->getParent()->end();
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if (++I == E)
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return nullptr;
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return I;
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return &*I;
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}
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/// ValidSimple - Returns true if the 'true' block (along with its
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@ -530,10 +530,10 @@ bool IfConverter::ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
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MachineBasicBlock *TExit = FalseBranch ? TrueBBI.FalseBB : TrueBBI.TrueBB;
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if (!TExit && blockAlwaysFallThrough(TrueBBI)) {
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MachineFunction::iterator I = TrueBBI.BB;
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MachineFunction::iterator I = TrueBBI.BB->getIterator();
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if (++I == TrueBBI.BB->getParent()->end())
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return false;
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TExit = I;
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TExit = &*I;
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}
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return TExit && TExit == FalseBBI.BB;
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}
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@ -948,10 +948,8 @@ void IfConverter::AnalyzeBlock(MachineBasicBlock *MBB,
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/// candidates.
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void IfConverter::AnalyzeBlocks(MachineFunction &MF,
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std::vector<IfcvtToken*> &Tokens) {
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *BB = I;
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AnalyzeBlock(BB, Tokens);
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}
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for (auto &BB : MF)
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AnalyzeBlock(&BB, Tokens);
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// Sort to favor more complex ifcvt scheme.
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std::stable_sort(Tokens.begin(), Tokens.end(), IfcvtTokenCmp);
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@ -961,14 +959,14 @@ void IfConverter::AnalyzeBlocks(MachineFunction &MF,
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/// that all the intervening blocks are empty (given BB can fall through to its
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/// next block).
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static bool canFallThroughTo(MachineBasicBlock *BB, MachineBasicBlock *ToBB) {
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MachineFunction::iterator PI = BB;
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MachineFunction::iterator PI = BB->getIterator();
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MachineFunction::iterator I = std::next(PI);
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MachineFunction::iterator TI = ToBB;
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MachineFunction::iterator TI = ToBB->getIterator();
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MachineFunction::iterator E = BB->getParent()->end();
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while (I != TI) {
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// Check isSuccessor to avoid case where the next block is empty, but
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// it's not a successor.
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if (I == E || !I->empty() || !PI->isSuccessor(I))
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if (I == E || !I->empty() || !PI->isSuccessor(&*I))
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return false;
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PI = I++;
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}
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@ -144,7 +144,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
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PrevPos = Start;
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}
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MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum);
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MachineFunction::const_iterator MFI =
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MF->getBlockNumbered(MBBNum)->getIterator();
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BlockInterference *BI = &Blocks[MBBNum];
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ArrayRef<SlotIndex> RegMaskSlots;
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ArrayRef<const uint32_t*> RegMaskBits;
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@ -75,7 +75,7 @@ static CallInst *ReplaceCallWith(const char *NewFn, CallInst *CI,
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Constant* FCache = M->getOrInsertFunction(NewFn,
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FunctionType::get(RetTy, ParamTys, false));
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IRBuilder<> Builder(CI->getParent(), CI);
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IRBuilder<> Builder(CI->getParent(), CI->getIterator());
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SmallVector<Value *, 8> Args(ArgBegin, ArgEnd);
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CallInst *NewCI = Builder.CreateCall(FCache, Args);
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NewCI->setName(CI->getName());
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@ -167,8 +167,8 @@ static Value *LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP) {
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assert(V->getType()->isIntegerTy() && "Can't bswap a non-integer type!");
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unsigned BitSize = V->getType()->getPrimitiveSizeInBits();
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IRBuilder<> Builder(IP->getParent(), IP);
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IRBuilder<> Builder(IP);
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switch(BitSize) {
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default: llvm_unreachable("Unhandled type size of value to byteswap!");
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@ -268,7 +268,7 @@ static Value *LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP) {
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0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
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};
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IRBuilder<> Builder(IP->getParent(), IP);
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IRBuilder<> Builder(IP);
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unsigned BitSize = V->getType()->getPrimitiveSizeInBits();
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unsigned WordSize = (BitSize + 63) / 64;
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@ -301,7 +301,7 @@ static Value *LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP) {
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/// instruction IP.
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static Value *LowerCTLZ(LLVMContext &Context, Value *V, Instruction *IP) {
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IRBuilder<> Builder(IP->getParent(), IP);
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IRBuilder<> Builder(IP);
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unsigned BitSize = V->getType()->getPrimitiveSizeInBits();
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for (unsigned i = 1; i < BitSize; i <<= 1) {
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@ -338,7 +338,7 @@ static void ReplaceFPIntrinsicWithCall(CallInst *CI, const char *Fname,
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}
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void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
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IRBuilder<> Builder(CI->getParent(), CI);
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IRBuilder<> Builder(CI);
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LLVMContext &Context = CI->getContext();
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const Function *Callee = CI->getCalledFunction();
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@ -512,7 +512,7 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
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bool Changed = false;
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for (MachineFunction::iterator MFI = mf.begin(), MFE = mf.end(); MFI != MFE;
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++MFI) {
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MachineBasicBlock *MBB = MFI;
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MachineBasicBlock *MBB = &*MFI;
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for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
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MBBI != MBBE;) {
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if (!MBBI->isDebugValue()) {
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@ -1004,11 +1004,11 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
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SlotIndex Stop = I.stop();
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unsigned LocNo = I.value();
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DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << LocNo);
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MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
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SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
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MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
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SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB);
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DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
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insertDebugValue(MBB, Start, LocNo, LIS, TII);
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insertDebugValue(&*MBB, Start, LocNo, LIS, TII);
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// This interval may span multiple basic blocks.
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// Insert a DBG_VALUE into each one.
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while(Stop > MBBEnd) {
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@ -1016,9 +1016,9 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
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Start = MBBEnd;
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if (++MBB == MFEnd)
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break;
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MBBEnd = LIS.getMBBEndIdx(MBB);
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MBBEnd = LIS.getMBBEndIdx(&*MBB);
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DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
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insertDebugValue(MBB, Start, LocNo, LIS, TII);
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insertDebugValue(&*MBB, Start, LocNo, LIS, TII);
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}
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DEBUG(dbgs() << '\n');
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if (MBB == MFEnd)
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@ -224,7 +224,7 @@ void LiveIntervals::computeRegMasks() {
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// Find all instructions with regmask operands.
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for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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MachineBasicBlock *MBB = &*MBBI;
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std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
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RMB.first = RegMaskSlots.size();
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for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
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@ -302,7 +302,7 @@ void LiveIntervals::computeLiveInRegUnits() {
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// Check all basic blocks for live-ins.
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for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
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MFI != MFE; ++MFI) {
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const MachineBasicBlock *MBB = MFI;
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const MachineBasicBlock *MBB = &*MFI;
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// We only care about ABI blocks: Entry + landing pads.
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if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
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@ -637,7 +637,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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// nodes, which are treated as a special case).
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MachineBasicBlock *Entry = MF->begin();
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MachineBasicBlock *Entry = &MF->front();
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SmallPtrSet<MachineBasicBlock*,16> Visited;
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for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
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@ -325,7 +325,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
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// Sort the frame references by local offset
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array_pod_sort(FrameReferenceInsns.begin(), FrameReferenceInsns.end());
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MachineBasicBlock *Entry = Fn.begin();
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MachineBasicBlock *Entry = &Fn.front();
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unsigned BaseReg = 0;
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int64_t BaseOffset = 0;
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