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[ARM] Expand v1i64 and v2i64 ctlz.
The default is legal, which results in 'Cannot select' errors. llvm-svn: 267520
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@ -580,6 +580,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
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setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
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setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
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setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
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// NEON does not have single instruction CTTZ for vectors.
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setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
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setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
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@ -44,6 +44,13 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vclz64(<1 x i64>* %A) nounwind {
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;CHECK-LABEL: vclz64:
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%tmp1 = load <1 x i64>, <1 x i64>* %A
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%tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 0)
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: vclzQ8:
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;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
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@ -68,13 +75,22 @@ define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vclzQ64(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vclzQ64:
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 0)
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ret <2 x i64> %tmp2
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}
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone
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declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
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declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
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declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
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declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
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define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vclss8:
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