RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-25 05:15:58 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Delete some unused instructions.

Browse Source 
llvm-svn: 110710
This commit is contained in:
Evan Cheng 2010-08-10 19:36:22 +00:00
parent d9a1b0d046
commit 784a286b92
3 changed files with 0 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4095,78 +4095,6 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
case ARM::tANDsp:
case ARM::tADDspr_:
case ARM::tSUBspi_:
case ARM::t2SUBrSPi_:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPs_: {
MachineFunction *MF = BB->getParent();
unsigned DstReg = MI->getOperand(0).getReg();
unsigned SrcReg = MI->getOperand(1).getReg();
bool DstIsDead = MI->getOperand(0).isDead();
bool SrcIsKill = MI->getOperand(1).isKill();
if (SrcReg != ARM::SP) {
// Copy the source to SP from virtual register.
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
.addReg(SrcReg, getKillRegState(SrcIsKill));
}
unsigned OpOpc = 0;
bool NeedPred = false, NeedCC = false, NeedOp3 = false;
switch (MI->getOpcode()) {
default:
llvm_unreachable("Unexpected pseudo instruction!");
case ARM::tANDsp:
OpOpc = ARM::tAND;
NeedPred = true;
break;
case ARM::tADDspr_:
OpOpc = ARM::tADDspr;
break;
case ARM::tSUBspi_:
OpOpc = ARM::tSUBspi;
break;
case ARM::t2SUBrSPi_:
OpOpc = ARM::t2SUBrSPi;
NeedPred = true; NeedCC = true;
break;
case ARM::t2SUBrSPi12_:
OpOpc = ARM::t2SUBrSPi12;
NeedPred = true;
break;
case ARM::t2SUBrSPs_:
OpOpc = ARM::t2SUBrSPs;
NeedPred = true; NeedCC = true; NeedOp3 = true;
break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
if (OpOpc == ARM::tAND)
AddDefaultT1CC(MIB);
MIB.addReg(ARM::SP);
MIB.addOperand(MI->getOperand(2));
if (NeedOp3)
MIB.addOperand(MI->getOperand(3));
if (NeedPred)
AddDefaultPred(MIB);
if (NeedCC)
AddDefaultCC(MIB);
// Copy the result from SP to virtual register.
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
BuildMI(*BB, MI, dl, TII->get(CopyOpc))
.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
.addReg(ARM::SP);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
}
}

13
lib/Target/ARM/ARMInstrThumb.td
View File

@ -251,19 +251,6 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
let Inst{2-0} = 0b101;
}
// Pseudo instruction that will expand into a tSUBspi + a copy.
let usesCustomInserter = 1 in { // Expanded after instruction selection.
def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
NoItinerary, "${:comment} sub\t$dst, $rhs", []>;
def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
NoItinerary, "${:comment} add\t$dst, $rhs", []>;
let Defs = [CPSR] in
def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
NoItinerary, "${:comment} and\t$dst, $rhs", []>;
} // usesCustomInserter
//===----------------------------------------------------------------------===//
// Control Flow Instructions.
//

14
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -888,20 +888,6 @@ def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
let Inst{7-4} = 0b1111;
}
// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
// FIXME: Now that we have rGPR, do we need these pseudos? It seems
// that the coalescer will now properly know how to do the right
// thing without them.
let usesCustomInserter = 1 in { // Expanded after instruction selection.
def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>;
def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>;
} // usesCustomInserter
//===----------------------------------------------------------------------===//
// Load / store Instructions.
//