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[RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supported

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When the compressed instruction set is enabled, the 16-bit c.nop can be
generated if necessary.

Differential Revision: https://reviews.llvm.org/D41221
Patch by Shiva Chen.

llvm-svn: 322658
This commit is contained in:
Alex Bradbury 2018-01-17 14:17:12 +00:00
parent 64e6cefd21
commit 787e68e0a3
2 changed files with 44 additions and 8 deletions
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26
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
View File

@ -27,12 +27,13 @@ using namespace llvm;
namespace {
class RISCVAsmBackend : public MCAsmBackend {
const MCSubtargetInfo &STI;
uint8_t OSABI;
bool Is64Bit;
public:
RISCVAsmBackend(uint8_t OSABI, bool Is64Bit)
: MCAsmBackend(), OSABI(OSABI), Is64Bit(Is64Bit) {}
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit)
: MCAsmBackend(), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit) {}
~RISCVAsmBackend() override {}
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
@ -88,15 +89,24 @@ public:
};
bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
// Once support for the compressed instruction set is added, we will be able
// to conditionally support 16-bit NOPs
if ((Count % 4) != 0)
bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
unsigned MinNopLen = HasStdExtC ? 2 : 4;
if ((Count % MinNopLen) != 0)
return false;
// The canonical nop on RISC-V is addi x0, x0, 0
for (uint64_t i = 0; i < Count; i += 4)
// The canonical nop on RISC-V is addi x0, x0, 0.
uint64_t Nop32Count = Count / 4;
for (uint64_t i = Nop32Count; i != 0; --i)
OW->write32(0x13);
// The canonical nop on RVC is c.nop.
if (HasStdExtC) {
uint64_t Nop16Count = (Count - Nop32Count * 4) / 2;
for (uint64_t i = Nop16Count; i != 0; --i)
OW->write16(0x01);
}
return true;
}
@ -235,5 +245,5 @@ MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit());
}

26
test/MC/RISCV/cnop.s Normal file
View File

@ -0,0 +1,26 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
# RUN: | llvm-objdump -mattr=+c -d - | FileCheck -check-prefix=CHECK-INST %s
# alpha and main are 8 byte alignment
# but the alpha function's size is 6
# So assembler will insert a c.nop to make sure 8 byte alignment.
.text
.p2align 3
.type alpha,@function
alpha:
# BB#0:
addi sp, sp, -16
c.lw a0, 0(a0)
# CHECK-INST: c.nop
.Lfunc_end0:
.size alpha, .Lfunc_end0-alpha
# -- End function
.globl main
.p2align 3
.type main,@function
main: # @main
# BB#0:
.Lfunc_end1:
.size main, .Lfunc_end1-main
# -- End function