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[DAGCombiner] Fix & simplify constant folding of sext/zext.
Summary: This patch fixes the cases of sext/zext constant folding in DAG combiner where constans do not fit 64 bits. The fix simply removes un$ Test Plan: New regression test included. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10607 llvm-svn: 240991
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@ -5579,12 +5579,12 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
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SDLoc(N));
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SDLoc(N));
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}
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}
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// tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
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/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
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// dag node into a ConstantSDNode or a build_vector of constants.
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/// a build_vector of constants.
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// This function is called by the DAGCombiner when visiting sext/zext/aext
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/// This function is called by the DAGCombiner when visiting sext/zext/aext
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// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
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/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
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// Vector extends are not folded if operations are legal; this is to
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/// Vector extends are not folded if operations are legal; this is to
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// avoid introducing illegal build_vector dag nodes.
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/// avoid introducing illegal build_vector dag nodes.
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static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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SelectionDAG &DAG, bool LegalTypes,
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SelectionDAG &DAG, bool LegalTypes,
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bool LegalOperations) {
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bool LegalOperations) {
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@ -5614,7 +5614,6 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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// We can fold this node into a build_vector.
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// We can fold this node into a build_vector.
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unsigned VTBits = SVT.getSizeInBits();
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unsigned VTBits = SVT.getSizeInBits();
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unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
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unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
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unsigned ShAmt = VTBits - EVTBits;
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SmallVector<SDValue, 8> Elts;
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SmallVector<SDValue, 8> Elts;
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumElts = VT.getVectorNumElements();
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SDLoc DL(N);
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SDLoc DL(N);
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@ -5627,14 +5626,13 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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}
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}
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SDLoc DL(Op);
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SDLoc DL(Op);
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ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
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// Get the constant value and if needed trunc it to the size of the type.
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const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
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// Nodes like build_vector might have constants wider than the scalar type.
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APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
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if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
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if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
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Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
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Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
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DL, SVT));
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else
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else
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Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
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Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT));
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DL, SVT));
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
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92
test/CodeGen/X86/fold-vector-sext-crash2.ll
Normal file
92
test/CodeGen/X86/fold-vector-sext-crash2.ll
Normal file
@ -0,0 +1,92 @@
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; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
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; DAGCombiner crashes during sext folding
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define <2 x i256> @test_sext1() {
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%Se = sext <2 x i8> <i8 -100, i8 -99> to <2 x i256>
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%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
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ret <2 x i256> %Shuff
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; X64-LABEL: test_sext1
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; X64: movq $-1
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; X64-NEXT: movq $-1
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; X64-NEXT: movq $-1
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; X64-NEXT: movq $-99
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; X32-LABEL: test_sext1
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; X32: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-99
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}
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define <2 x i256> @test_sext2() {
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%Se = sext <2 x i128> <i128 -2000, i128 -1999> to <2 x i256>
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%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
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ret <2 x i256> %Shuff
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; X64-LABEL: test_sext2
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; X64: movq $-1
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; X64-NEXT: movq $-1
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; X64-NEXT: movq $-1
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; X64-NEXT: movq $-1999
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; X32-LABEL: test_sext2
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; X32: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1999
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}
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define <2 x i256> @test_zext1() {
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%Se = zext <2 x i8> <i8 -1, i8 -2> to <2 x i256>
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%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
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ret <2 x i256> %Shuff
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; X64-LABEL: test_zext1
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; X64: movq $0
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; X64-NEXT: movq $0
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; X64-NEXT: movq $0
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; X64-NEXT: movq $254
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; X32-LABEL: test_zext1
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; X32: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $254
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}
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define <2 x i256> @test_zext2() {
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%Se = zext <2 x i128> <i128 -1, i128 -2> to <2 x i256>
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%Shuff = shufflevector <2 x i256> zeroinitializer, <2 x i256> %Se, <2 x i32> <i32 1, i32 3>
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ret <2 x i256> %Shuff
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; X64-LABEL: test_zext2
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; X64: movq $0
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; X64-NEXT: movq $0
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; X64-NEXT: movq $-1
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; X64-NEXT: movq $-2
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; X32-LABEL: test_zext2
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; X32: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $0
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-1
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; X32-NEXT: movl $-2
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}
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