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[AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portion

Browse Source 
https://reviews.llvm.org/D42993

llvm-svn: 324912
This commit is contained in:
Abderrazek Zaafrani 2018-02-12 17:35:42 +00:00
parent c7c90124a2
commit 788c698674
2 changed files with 36 additions and 0 deletions
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6
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -3530,6 +3530,8 @@ def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
(FCVTPUv1i64 FPR64:$Rn)>;
def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))),
(FRECPEv1f16 FPR16:$Rn)>;
def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
(FRECPEv1i32 FPR32:$Rn)>;
def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
@ -3561,11 +3563,15 @@ def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
(FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;
def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))),
(FRECPXv1f16 FPR16:$Rn)>;
def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
(FRECPXv1i32 FPR32:$Rn)>;
def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
(FRECPXv1i64 FPR64:$Rn)>;
def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))),
(FRSQRTEv1f16 FPR16:$Rn)>;
def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
(FRSQRTEv1i32 FPR32:$Rn)>;
def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),

30
test/CodeGen/AArch64/f16-instructions.ll
View File

@ -736,6 +736,9 @@ declare half @llvm.rint.f16(half %a) #0
declare half @llvm.nearbyint.f16(half %a) #0
declare half @llvm.round.f16(half %a) #0
declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
declare half @llvm.aarch64.neon.frecpe.f16(half %a) #0
declare half @llvm.aarch64.neon.frecpx.f16(half %a) #0
declare half @llvm.aarch64.neon.frsqrte.f16(half %a) #0
; CHECK-CVT-LABEL: test_sqrt:
; CHECK-CVT-NEXT: fcvt s0, h0
@ -1124,4 +1127,31 @@ define half @test_fmuladd(half %a, half %b, half %c) #0 {
ret half %r
}
; CHECK-FP16-LABEL: test_vrecpeh_f16:
; CHECK-FP16-NEXT: frecpe h0, h0
; CHECK-FP16-NEXT: ret
define half @test_vrecpeh_f16(half %a) #0 {
%r = call half @llvm.aarch64.neon.frecpe.f16(half %a)
ret half %r
}
; CHECK-FP16-LABEL: test_vrecpxh_f16:
; CHECK-FP16-NEXT: frecpx h0, h0
; CHECK-FP16-NEXT: ret
define half @test_vrecpxh_f16(half %a) #0 {
%r = call half @llvm.aarch64.neon.frecpx.f16(half %a)
ret half %r
}
; CHECK-FP16-LABEL: test_vrsqrteh_f16:
; CHECK-FP16-NEXT: frsqrte h0, h0
; CHECK-FP16-NEXT: ret
define half @test_vrsqrteh_f16(half %a) #0 {
%r = call half @llvm.aarch64.neon.frsqrte.f16(half %a)
ret half %r
}
attributes #0 = { nounwind }