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Fix spelling.
llvm-svn: 190749
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@ -4201,7 +4201,7 @@ breakPartialRegDependency(MachineBasicBlock::iterator MI,
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// FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
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// the full D-register by loading the same value to both lanes. The
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// instruction is micro-coded with 2 uops, so don't do this until we can
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// properly schedule micro-coded instuctions. The dispatcher stalls cause
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// properly schedule micro-coded instructions. The dispatcher stalls cause
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// too big regressions.
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// Insert the dependency-breaking FCONSTD before MI.
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