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Revert unapproved commit
llvm-svn: 347511
This commit is contained in:
Joel Jones
parent
74a51d699d
commit
78f772fee0
@ -47,7 +47,6 @@ struct VecDesc {
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class TargetLibraryInfoImpl {
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friend class TargetLibraryInfo;
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Triple TT;
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unsigned char AvailableArray[(NumLibFuncs+3)/4];
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llvm::DenseMap<unsigned, std::string> CustomNames;
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static StringRef const StandardNames[NumLibFuncs];
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@ -88,8 +87,7 @@ public:
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enum VectorLibrary {
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NoLibrary, // Don't use any vector library.
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Accelerate, // Use Accelerate framework.
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SVML, // Intel short vector math library.
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SLEEFGNUABI // SLEEF - SIMD Library for Evaluating Elementary Functions.
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SVML // Intel short vector math library.
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};
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TargetLibraryInfoImpl();
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@ -430,34 +430,14 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable] in {
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def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
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def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_acos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_asin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_atan : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_atan2 : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>]>;
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def int_tan : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_pow : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>]>;
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def int_cosh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_sinh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_tanh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_asinh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_acosh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_atanh : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_lgamma : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_tgamma : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_exp10 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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def int_copysign : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>]>;
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def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
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@ -25,9 +25,7 @@ static cl::opt<TargetLibraryInfoImpl::VectorLibrary> ClVectorLibrary(
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clEnumValN(TargetLibraryInfoImpl::Accelerate, "Accelerate",
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"Accelerate framework"),
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clEnumValN(TargetLibraryInfoImpl::SVML, "SVML",
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"Intel SVML library"),
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clEnumValN(TargetLibraryInfoImpl::SLEEFGNUABI, "sleefgnuabi",
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"SIMD Library for Evaluating Elementary Functions")));
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"Intel SVML library")));
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StringRef const TargetLibraryInfoImpl::StandardNames[LibFunc::NumLibFuncs] = {
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#define TLI_DEFINE_STRING
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@ -526,8 +524,7 @@ TargetLibraryInfoImpl::TargetLibraryInfoImpl() {
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initialize(*this, Triple(), StandardNames);
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}
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TargetLibraryInfoImpl::TargetLibraryInfoImpl(const Triple &T)
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: TT(T) {
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TargetLibraryInfoImpl::TargetLibraryInfoImpl(const Triple &T) {
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// Default to everything being available.
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memset(AvailableArray, -1, sizeof(AvailableArray));
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@ -535,8 +532,7 @@ TargetLibraryInfoImpl::TargetLibraryInfoImpl(const Triple &T)
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}
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TargetLibraryInfoImpl::TargetLibraryInfoImpl(const TargetLibraryInfoImpl &TLI)
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: TT(TLI.TT), CustomNames(TLI.CustomNames),
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ShouldExtI32Param(TLI.ShouldExtI32Param),
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: CustomNames(TLI.CustomNames), ShouldExtI32Param(TLI.ShouldExtI32Param),
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ShouldExtI32Return(TLI.ShouldExtI32Return),
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ShouldSignExtI32Param(TLI.ShouldSignExtI32Param) {
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memcpy(AvailableArray, TLI.AvailableArray, sizeof(AvailableArray));
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@ -545,7 +541,7 @@ TargetLibraryInfoImpl::TargetLibraryInfoImpl(const TargetLibraryInfoImpl &TLI)
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}
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TargetLibraryInfoImpl::TargetLibraryInfoImpl(TargetLibraryInfoImpl &&TLI)
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: TT(std::move(TLI.TT)), CustomNames(std::move(TLI.CustomNames)),
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: CustomNames(std::move(TLI.CustomNames)),
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ShouldExtI32Param(TLI.ShouldExtI32Param),
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ShouldExtI32Return(TLI.ShouldExtI32Return),
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ShouldSignExtI32Param(TLI.ShouldSignExtI32Param) {
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@ -556,7 +552,6 @@ TargetLibraryInfoImpl::TargetLibraryInfoImpl(TargetLibraryInfoImpl &&TLI)
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}
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TargetLibraryInfoImpl &TargetLibraryInfoImpl::operator=(const TargetLibraryInfoImpl &TLI) {
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TT = TLI.TT;
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CustomNames = TLI.CustomNames;
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ShouldExtI32Param = TLI.ShouldExtI32Param;
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ShouldExtI32Return = TLI.ShouldExtI32Return;
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@ -566,7 +561,6 @@ TargetLibraryInfoImpl &TargetLibraryInfoImpl::operator=(const TargetLibraryInfoI
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}
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TargetLibraryInfoImpl &TargetLibraryInfoImpl::operator=(TargetLibraryInfoImpl &&TLI) {
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TT = std::move(TLI.TT);
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CustomNames = std::move(TLI.CustomNames);
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ShouldExtI32Param = TLI.ShouldExtI32Param;
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ShouldExtI32Return = TLI.ShouldExtI32Return;
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@ -1585,150 +1579,6 @@ void TargetLibraryInfoImpl::addVectorizableFunctionsFromVecLib(
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addVectorizableFunctions(VecFuncs);
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break;
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}
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case SLEEFGNUABI: {
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if (TT.getArch() == llvm::Triple::aarch64 ||
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TT.getArch() == llvm::Triple::aarch64_be) {
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const VecDesc AArch64TwoAndFourLaneVecFuncs[] = {
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{ "acos", "_ZGVnN2v_acos", 2 },
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{ "acos", "_ZGVnN4v_acosf", 4 },
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{ "acosf", "_ZGVnN4v_acosf", 4 },
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{ "llvm.acos.f64", "_ZGVnN2v_acos", 2 },
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{ "llvm.acos.f32", "_ZGVnN4v_acosf", 4 },
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{ "asin", "_ZGVnN2v_asin", 2 },
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{ "asin", "_ZGVnN4v_asinf", 4 },
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{ "asinf", "_ZGVnN4v_asinf", 4 },
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{ "llvm.asin.f64", "_ZGVnN2v_asin", 2 },
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{ "llvm.asin.f32", "_ZGVnN4v_asinf", 4 },
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{ "atan", "_ZGVnN2v_atan", 2 },
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{ "atan", "_ZGVnN4v_atanf", 4 },
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{ "atanf", "_ZGVnN4v_atanf", 4 },
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{ "llvm.atan.f64", "_ZGVnN2v_atan", 2 },
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{ "llvm.atan.f32", "_ZGVnN4v_atanf", 4 },
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{ "atan2", "_ZGVnN2vv_atan2", 2 },
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{ "atan2", "_ZGVnN4vv_atan2f", 4 },
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{ "atan2f", "_ZGVnN4vv_atan2f", 4 },
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{ "llvm.atan2.f64", "_ZGVnN2vv_atan2", 2 },
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{ "llvm.atan2.f32", "_ZGVnN4vv_atan2f", 4 },
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{ "llvm.atan2.v2f64", "_ZGVnN2vv_atan2", 2 },
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{ "llvm.atan2.v4f32", "_ZGVnN4vv_atan2f", 4 },
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{ "atanh", "_ZGVnN2v_atanh", 2 },
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{ "atanh", "_ZGVnN4v_atanhf", 4 },
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{ "atanhf", "_ZGVnN4v_atanhf", 4 },
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{ "llvm.atanh.f64", "_ZGVnN2v_atanh", 2 },
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{ "llvm.atanh.f32", "_ZGVnN4v_atanhf", 4 },
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{ "cos", "_ZGVnN2v_cos", 2 },
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{ "cos", "_ZGVnN4v_cosf", 4 },
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{ "cosf", "_ZGVnN4v_cosf", 4 },
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{ "llvm.cos.f64", "_ZGVnN2v_cos", 2 },
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{ "llvm.cos.f32", "_ZGVnN4v_cosf", 4 },
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{ "cosh", "_ZGVnN2v_cosh", 2 },
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{ "cosh", "_ZGVnN4v_coshf", 4 },
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{ "coshf", "_ZGVnN4v_coshf", 4 },
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{ "llvm.cosh.f64", "_ZGVnN2v_cosh", 2 },
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{ "llvm.cosh.f32", "_ZGVnN4v_coshf", 4 },
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{ "exp", "_ZGVnN2v_exp", 2 },
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{ "exp", "_ZGVnN4v_expf", 4 },
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{ "expf", "_ZGVnN4v_expf", 4 },
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{ "llvm.exp.f64", "_ZGVnN2v_exp", 2 },
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{ "llvm.exp.f32", "_ZGVnN4v_expf", 4 },
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{ "llvm.exp.v2f64", "_ZGVnN2v_exp", 2 },
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{ "llvm.exp.v4f32", "_ZGVnN4v_expf", 4 },
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{ "exp2", "_ZGVnN2v_exp2", 2 },
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{ "exp2", "_ZGVnN4v_exp2f", 4 },
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{ "exp2f", "_ZGVnN4v_exp2f", 4 },
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{ "llvm.exp2.f64", "_ZGVnN2v_exp2", 2 },
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{ "llvm.exp2.f32", "_ZGVnN4v_exp2f", 4 },
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{ "llvm.exp2.v2f64", "_ZGVnN2v_exp2", 2 },
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{ "llvm.exp2.v4f32", "_ZGVnN4v_exp2f", 4 },
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{ "exp10", "_ZGVnN2v_exp10", 2 },
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{ "exp10", "_ZGVnN4v_exp10f", 4 },
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{ "exp10f", "_ZGVnN4v_exp10f", 4 },
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{ "llvm.exp10.f64", "_ZGVnN2v_exp10", 2 },
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{ "llvm.exp10.f32", "_ZGVnN4v_exp10f", 4 },
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{ "llvm.exp10.v2f64", "_ZGVnN2v_exp10", 2 },
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{ "llvm.exp10.v4f32", "_ZGVnN4v_exp10f", 4 },
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{ "lgamma", "_ZGVnN2v_lgamma", 2 },
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{ "lgamma", "_ZGVnN4v_lgammaf", 4 },
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{ "lgammaf", "_ZGVnN4v_lgammaf", 4 },
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{ "llvm.lgamma.f64", "_ZGVnN2v_lgamma", 2 },
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{ "llvm.lgamma.f32", "_ZGVnN4v_lgammaf", 4 },
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{ "log", "_ZGVnN2v_log", 2 },
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{ "log", "_ZGVnN4v_logf", 4 },
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{ "logf", "_ZGVnN4v_logf", 4 },
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{ "llvm.log.f64", "_ZGVnN2v_log", 2 },
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{ "llvm.log.f32", "_ZGVnN4v_logf", 4 },
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{ "log2", "_ZGVnN2v_log2", 2 },
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{ "log2", "_ZGVnN4v_log2f", 4 },
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{ "log2f", "_ZGVnN4v_log2f", 4 },
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{ "llvm.log2.f64", "_ZGVnN2v_log2", 2 },
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{ "llvm.log2.f32", "_ZGVnN4v_log2f", 4 },
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{ "log10", "_ZGVnN2v_log10", 2 },
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{ "log10", "_ZGVnN4v_log10f", 4 },
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{ "log10f", "_ZGVnN4v_log10f", 4 },
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{ "llvm.log10.f64", "_ZGVnN2v_log10", 2 },
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{ "llvm.log10.f32", "_ZGVnN4v_log10f", 4 },
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{ "pow", "_ZGVnN2vv_pow", 2 },
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{ "pow", "_ZGVnN4vv_powf", 4 },
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{ "powf", "_ZGVnN4vv_powf", 4 },
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{ "llvm.pow.f64", "_ZGVnN2vv_pow", 2 },
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{ "llvm.pow.f32", "_ZGVnN4vv_powf", 4 },
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{ "llvm.pow.v2f64", "_ZGVnN2vv_pow", 2 },
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{ "llvm.pow.v4f32", "_ZGVnN4vv_powf", 4 },
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{ "sin", "_ZGVnN2v_sin", 2 },
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{ "sin", "_ZGVnN4v_sinf", 4 },
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{ "sinf", "_ZGVnN4v_sinf", 4 },
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{ "llvm.sin.f64", "_ZGVnN2v_sin", 2 },
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{ "llvm.sin.f32", "_ZGVnN4v_sinf", 4 },
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{ "sinh", "_ZGVnN2v_sinh", 2 },
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{ "sinh", "_ZGVnN4v_sinhf", 4 },
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{ "sinhf", "_ZGVnN4v_sinhf", 4 },
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{ "llvm.sinh.f64", "_ZGVnN2v_sinh", 2 },
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{ "llvm.sinh.f32", "_ZGVnN4v_sinhf", 4 },
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{ "sqrt", "_ZGVnN2v_sqrt", 2 },
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{ "sqrt", "_ZGVnN4v_sqrtf", 4 },
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{ "sqrtf", "_ZGVnN4v_sqrtf", 4 },
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{ "llvm.sqrt.f64", "_ZGVnN2v_sqrt", 2 },
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{ "llvm.sqrt.f32", "_ZGVnN4v_sqrtf", 4 },
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{ "tan", "_ZGVnN2v_tan", 2 },
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{ "tan", "_ZGVnN4v_tanf", 4 },
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{ "tanf", "_ZGVnN4v_tanf", 4 },
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{ "llvm.tan.f64", "_ZGVnN2v_tan", 2 },
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{ "llvm.tan.f32", "_ZGVnN4v_tanf", 4 },
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{ "tanh", "_ZGVnN2v_tanh", 2 },
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{ "tanh", "_ZGVnN4v_tanhf", 4 },
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{ "tanhf", "_ZGVnN4v_tanhf", 4 },
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{ "llvm.tanh.f64", "_ZGVnN2v_tanh", 2 },
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{ "llvm.tanh.f32", "_ZGVnN4v_tanhf", 4 },
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{ "tgamma", "_ZGVnN2v_tgamma", 2 },
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{ "tgamma", "_ZGVnN4v_tgammaf", 4 },
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{ "tgammaf", "_ZGVnN4v_tgammaf", 4 },
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{ "llvm.tgamma.f64", "_ZGVnN2v_tgamma", 2 },
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{ "llvm.tgamma.f32", "_ZGVnN4v_tgammaf", 4 },
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};
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addVectorizableFunctions(AArch64TwoAndFourLaneVecFuncs);
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}
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break;
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}
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case NoLibrary:
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break;
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}
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