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Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the

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LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type

We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]

llvm-svn: 147251
This commit is contained in:
Chandler Carruth 2011-12-24 12:12:34 +00:00
parent 82b7a7478b
commit 7a5c52fadf
4 changed files with 19 additions and 23 deletions
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32
lib/Target/X86/X86ISelLowering.cpp
View File

@ -379,25 +379,31 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::FREM , MVT::f80 , Expand);
setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
// Promote the i8 variants and force them on up to i32 which has a shorter
// encoding.
setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
if (Subtarget->hasBMI()) {
setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
if (Subtarget->is64Bit())
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
} else {
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , Promote);
if (Subtarget->is64Bit())
setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
}
if (Subtarget->hasLZCNT()) {
// When promoting the i8 variants, force them to i32 for a shorter
// encoding.
setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Expand);
AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
if (Subtarget->is64Bit())
@ -9876,32 +9882,22 @@ SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
EVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
if (VT == MVT::i8) {
OpVT = MVT::i32;
Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsf (scan bits forward) which also sets EFLAGS.
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
// If src is zero (i.e. bsf sets ZF), returns NumBits.
SDValue Ops[] = {
Op,
DAG.getConstant(NumBits, OpVT),
DAG.getConstant(NumBits, VT),
DAG.getConstant(X86::COND_E, MVT::i8),
Op.getValue(1)
};
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
if (VT == MVT::i8)
Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
return Op;
return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
}
// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit

4
test/CodeGen/X86/bmi.ll
View File

@ -9,7 +9,7 @@ define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
ret i8 %tmp
; CHECK: t1:
; CHECK: tzcntw
; CHECK: tzcntl
}
define i16 @t2(i16 %x) nounwind {
@ -37,7 +37,7 @@ define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
; CHECK: t5:
; CHECK: tzcntw
; CHECK: tzcntl
}
define i16 @t6(i16 %x) nounwind {

2
test/CodeGen/X86/clz.ll
View File

@ -13,7 +13,7 @@ define i8 @cttz_i8(i8 %x) {
%tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
; CHECK: cttz_i8:
; CHECK: bsfw
; CHECK: bsfl
; CHECK-NOT: cmov
; CHECK: ret
}

4
test/CodeGen/X86/lzcnt.ll
View File

@ -9,7 +9,7 @@ define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
ret i8 %tmp
; CHECK: t1:
; CHECK: lzcntw
; CHECK: lzcntl
}
define i16 @t2(i16 %x) nounwind {
@ -37,7 +37,7 @@ define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp
; CHECK: t5:
; CHECK: lzcntw
; CHECK: lzcntl
}
define i16 @t6(i16 %x) nounwind {