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[AArch64] Implement FP16FML intrinsics
Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a DAG pattern to define the indexed-form intrinsics in terms of the vector-form ones, similarly to how the Dot Product intrinsics were implemented. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53632 llvm-svn: 345337
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Bryan Chan
parent
9d4ed39735
commit
7c08c135e3
@ -160,6 +160,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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class AdvSIMD_FP16FML_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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}
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// Arithmetic ops
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@ -430,6 +435,12 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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// v8.2-A Dot Product
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def int_aarch64_neon_udot : AdvSIMD_Dot_Intrinsic;
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def int_aarch64_neon_sdot : AdvSIMD_Dot_Intrinsic;
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// v8.2-A FP16 Fused Multiply-Add Long
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def int_aarch64_neon_fmlal : AdvSIMD_FP16FML_Intrinsic;
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def int_aarch64_neon_fmlsl : AdvSIMD_FP16FML_Intrinsic;
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def int_aarch64_neon_fmlal2 : AdvSIMD_FP16FML_Intrinsic;
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def int_aarch64_neon_fmlsl2 : AdvSIMD_FP16FML_Intrinsic;
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}
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let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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@ -4941,14 +4941,27 @@ class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<3> size, bits<5> opcode,
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let Inst{4-0} = Rd;
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}
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let Predicates = [HasNEON, HasFP16FML] in
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// ARMv8.2 Fused Multiply Add Long Instructions (Vector)
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class BaseSIMDThreeSameMult<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
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string kind2> :
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BaseSIMDThreeSameVector<Q, U, size, 0b11101, V128, asm, kind1, [] > {
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string kind2, RegisterOperand RegType,
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ValueType AccumType, ValueType InputType,
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SDPatternOperator OpNode> :
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BaseSIMDThreeSameVectorTied<Q, U, size, 0b11101, RegType, asm, kind1,
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[(set (AccumType RegType:$dst),
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(OpNode (AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType RegType:$Rm)))]> {
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let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
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let Inst{13} = b13;
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}
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multiclass SIMDThreeSameMult<bit U, bit b13, bits<3> size, string asm, SDPatternOperator OpNode> {
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def v4f16 : BaseSIMDThreeSameMult<0, U, b13, size, asm, ".2s", ".2h", V64,
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v2f32, v4f16, OpNode>;
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def v8f16 : BaseSIMDThreeSameMult<1, U, b13, size, asm, ".4s", ".4h", V128,
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v4f32, v8f16, OpNode>;
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}
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class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,
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string kind2, RegisterOperand RegType,
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ValueType AccumType, ValueType InputType,
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@ -7433,14 +7446,20 @@ class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string dst_kind,
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let Inst{11} = idx{1}; // H
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}
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let Predicates = [HasNEON, HasFP16FML] in
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// ARMv8.2 Fused Multiply Add Long Instructions (Indexed)
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class BaseSIMDThreeSameMultIndex<bit Q, bit U, bits<4> opc, string asm,
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string dst_kind, string lhs_kind,
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string rhs_kind> :
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BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, V128, V128, V128,
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VectorIndexH, asm, "", dst_kind, lhs_kind,
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rhs_kind, []> {
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//idx = H:L:M
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string rhs_kind, RegisterOperand RegType,
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ValueType AccumType, ValueType InputType,
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SDPatternOperator OpNode> :
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BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
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VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
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[(set (AccumType RegType:$dst),
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(AccumType (OpNode (AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType (AArch64duplane16 (v8f16 V128:$Rm),
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VectorIndexH:$idx)))))]> {
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// idx = H:L:M
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bits<3> idx;
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let Inst{11} = idx{2}; // H
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let Inst{21} = idx{1}; // L
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@ -7455,6 +7474,13 @@ multiclass SIMDThreeSameVectorDotIndex<bit U, string asm,
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v4i32, v16i8, OpNode>;
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}
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multiclass SIMDThreeSameMultIndex<bit U, bits<4> opc, string asm, SDPatternOperator OpNode> {
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def v4f16 : BaseSIMDThreeSameMultIndex<0, U, opc, asm, ".2s", ".2h", ".h", V64,
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v2f32, v4f16, OpNode>;
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def v8f16 : BaseSIMDThreeSameMultIndex<1, U, opc, asm, ".4s", ".4h", ".h", V128,
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v4f32, v8f16, OpNode>;
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}
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multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
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SDPatternOperator OpNode> {
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let Predicates = [HasNEON, HasFullFP16] in {
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@ -3463,22 +3463,16 @@ defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
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int_aarch64_neon_sqsub>;
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// FP16FML
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def FMLAL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b001, "fmlal", ".2s", ".2h">;
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def FMLSL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b101, "fmlsl", ".2s", ".2h">;
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def FMLAL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b001, "fmlal", ".4s", ".4h">;
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def FMLSL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b101, "fmlsl", ".4s", ".4h">;
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def FMLAL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b001, "fmlal2", ".2s", ".2h">;
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def FMLSL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b101, "fmlsl2", ".2s", ".2h">;
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def FMLAL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b001, "fmlal2", ".4s", ".4h">;
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def FMLSL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b101, "fmlsl2", ".4s", ".4h">;
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def FMLALI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0000, "fmlal", ".2s", ".2h", ".h">;
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def FMLSLI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0100, "fmlsl", ".2s", ".2h", ".h">;
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def FMLALI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0000, "fmlal", ".4s", ".4h", ".h">;
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def FMLSLI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0100, "fmlsl", ".4s", ".4h", ".h">;
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def FMLALI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1000, "fmlal2", ".2s", ".2h", ".h">;
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def FMLSLI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1100, "fmlsl2", ".2s", ".2h", ".h">;
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def FMLALI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1000, "fmlal2", ".4s", ".4h", ".h">;
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def FMLSLI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1100, "fmlsl2", ".4s", ".4h", ".h">;
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let Predicates = [HasNEON, HasFP16FML] in {
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defm FMLAL : SIMDThreeSameMult<0, 1, 0b001, "fmlal", int_aarch64_neon_fmlal>;
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defm FMLSL : SIMDThreeSameMult<0, 1, 0b101, "fmlsl", int_aarch64_neon_fmlsl>;
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defm FMLAL2 : SIMDThreeSameMult<1, 0, 0b001, "fmlal2", int_aarch64_neon_fmlal2>;
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defm FMLSL2 : SIMDThreeSameMult<1, 0, 0b101, "fmlsl2", int_aarch64_neon_fmlsl2>;
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defm FMLALlane : SIMDThreeSameMultIndex<0, 0b0000, "fmlal", int_aarch64_neon_fmlal>;
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defm FMLSLlane : SIMDThreeSameMultIndex<0, 0b0100, "fmlsl", int_aarch64_neon_fmlsl>;
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defm FMLAL2lane : SIMDThreeSameMultIndex<1, 0b1000, "fmlal2", int_aarch64_neon_fmlal2>;
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defm FMLSL2lane : SIMDThreeSameMultIndex<1, 0b1100, "fmlsl2", int_aarch64_neon_fmlsl2>;
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}
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defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
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defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
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74
test/CodeGen/AArch64/neon-fp16fml.ll
Normal file
74
test/CodeGen/AArch64/neon-fp16fml.ll
Normal file
@ -0,0 +1,74 @@
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; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+fp16fml < %s | FileCheck %s
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declare <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
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declare <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
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declare <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
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declare <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>)
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declare <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>)
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declare <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>)
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declare <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>)
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declare <4 x float> @llvm.aarch64.neon.fmlsl2.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>)
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define <2 x float> @test_vfmlal_low_u32(<2 x float> %a, <4 x half> %b, <4 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlal_low_u32:
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; CHECK: fmlal v0.2s, v1.2h, v2.2h
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%vfmlal_low2.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %a, <4 x half> %b, <4 x half> %c) #2
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ret <2 x float> %vfmlal_low2.i
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}
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define <2 x float> @test_vfmlsl_low_u32(<2 x float> %a, <4 x half> %b, <4 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlsl_low_u32:
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; CHECK: fmlsl v0.2s, v1.2h, v2.2h
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%vfmlsl_low2.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %a, <4 x half> %b, <4 x half> %c) #2
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ret <2 x float> %vfmlsl_low2.i
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}
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define <2 x float> @test_vfmlal_high_u32(<2 x float> %a, <4 x half> %b, <4 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlal_high_u32:
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; CHECK: fmlal2 v0.2s, v1.2h, v2.2h
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%vfmlal_high2.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %a, <4 x half> %b, <4 x half> %c) #2
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ret <2 x float> %vfmlal_high2.i
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}
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define <2 x float> @test_vfmlsl_high_u32(<2 x float> %a, <4 x half> %b, <4 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlsl_high_u32:
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; CHECK: fmlsl2 v0.2s, v1.2h, v2.2h
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%vfmlsl_high2.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %a, <4 x half> %b, <4 x half> %c) #2
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ret <2 x float> %vfmlsl_high2.i
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}
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define <4 x float> @test_vfmlalq_low_u32(<4 x float> %a, <8 x half> %b, <8 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlalq_low_u32:
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; CHECK: fmlal v0.4s, v1.4h, v2.4h
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%vfmlalq_low4.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %a, <8 x half> %b, <8 x half> %c) #2
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ret <4 x float> %vfmlalq_low4.i
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}
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define <4 x float> @test_vfmlslq_low_u32(<4 x float> %a, <8 x half> %b, <8 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlslq_low_u32:
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; CHECK: fmlsl v0.4s, v1.4h, v2.4h
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%vfmlslq_low4.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %a, <8 x half> %b, <8 x half> %c) #2
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ret <4 x float> %vfmlslq_low4.i
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}
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define <4 x float> @test_vfmlalq_high_u32(<4 x float> %a, <8 x half> %b, <8 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlalq_high_u32:
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; CHECK: fmlal2 v0.4s, v1.4h, v2.4h
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%vfmlalq_high4.i = call <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float> %a, <8 x half> %b, <8 x half> %c) #2
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ret <4 x float> %vfmlalq_high4.i
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}
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define <4 x float> @test_vfmlslq_high_u32(<4 x float> %a, <8 x half> %b, <8 x half> %c) #0 {
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entry:
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; CHECK-LABEL: test_vfmlslq_high_u32:
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; CHECK: fmlsl2 v0.4s, v1.4h, v2.4h
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%vfmlslq_high4.i = call <4 x float> @llvm.aarch64.neon.fmlsl2.v4f32.v8f16(<4 x float> %a, <8 x half> %b, <8 x half> %c) #2
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ret <4 x float> %vfmlslq_high4.i
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}
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