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[LV] Add abs/smin/smax/umin/umax intrinsics to isTriviallyVectorizable
This patch adds support for vectorizing these intrinsics. Differential Revision: https://reviews.llvm.org/D84796
This commit is contained in:
Craig Topper
parent
6d7e104f99
commit
7c95515f0a
@ -43,13 +43,18 @@ static cl::opt<unsigned> MaxInterleaveGroupFactor(
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/// hasVectorInstrinsicScalarOpd).
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bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
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switch (ID) {
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case Intrinsic::bswap: // Begin integer bit-manipulation.
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case Intrinsic::abs: // Begin integer bit-manipulation.
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case Intrinsic::bswap:
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case Intrinsic::bitreverse:
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case Intrinsic::ctpop:
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case Intrinsic::ctlz:
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case Intrinsic::cttz:
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case Intrinsic::fshl:
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case Intrinsic::fshr:
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case Intrinsic::smax:
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case Intrinsic::smin:
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case Intrinsic::umax:
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case Intrinsic::umin:
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case Intrinsic::sadd_sat:
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case Intrinsic::ssub_sat:
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case Intrinsic::uadd_sat:
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@ -94,6 +99,7 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
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bool llvm::hasVectorInstrinsicScalarOpd(Intrinsic::ID ID,
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unsigned ScalarOpdIdx) {
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switch (ID) {
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case Intrinsic::abs:
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case Intrinsic::ctlz:
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case Intrinsic::cttz:
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case Intrinsic::powi:
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@ -1244,6 +1244,136 @@ for.end: ; preds = %for.body, %entry
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ret void
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}
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declare i64 @llvm.abs.i64 (i64, i1) nounwind readnone
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define void @abs_i64(i32 %n, i64* noalias %y, i64* noalias %x) nounwind uwtable {
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;CHECK-LABEL: @abs_i64(
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;CHECK: llvm.abs.v4i64(<4 x i64> [[WIDE_LOADX:%.*]], i1 true)
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;CHECK: ret void
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entry:
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%cmp9 = icmp sgt i32 %n, 0
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br i1 %cmp9, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i64, i64* %y, i64 %indvars.iv
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%0 = load i64, i64* %arrayidx, align 8
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%call = tail call i64 @llvm.abs.i64(i64 %0, i1 true) nounwind readnone
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%arrayidx4 = getelementptr inbounds i64, i64* %x, i64 %indvars.iv
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store i64 %call, i64* %arrayidx4, align 8
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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declare i32 @llvm.smin.i32 (i32, i32)
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define void @smin_i32(i32 %n, i32* noalias %x, i32* noalias %y) {
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; CHECK-LABEL: @smin_i32(
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; CHECK: call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]])
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; CHECK: ret void
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %loop, label %end
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%xi = getelementptr inbounds i32, i32* %x, i32 %iv
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%yi = getelementptr inbounds i32, i32* %y, i32 %iv
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%xld = load i32, i32* %xi, align 4
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%yld = load i32, i32* %yi, align 4
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%call = tail call i32 @llvm.smin.i32(i32 %xld, i32 %yld)
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store i32 %call, i32* %xi, align 4
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%iv.next = add i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, %n
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br i1 %exitcond, label %end, label %loop
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end:
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ret void
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}
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declare i32 @llvm.smax.i32 (i32, i32)
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define void @smax_i32(i32 %n, i32* noalias %x, i32* noalias %y) {
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; CHECK-LABEL: @smax_i32(
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; CHECK: call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]])
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; CHECK: ret void
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %loop, label %end
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%xi = getelementptr inbounds i32, i32* %x, i32 %iv
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%yi = getelementptr inbounds i32, i32* %y, i32 %iv
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%xld = load i32, i32* %xi, align 4
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%yld = load i32, i32* %yi, align 4
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%call = tail call i32 @llvm.smax.i32(i32 %xld, i32 %yld)
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store i32 %call, i32* %xi, align 4
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%iv.next = add i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, %n
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br i1 %exitcond, label %end, label %loop
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end:
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ret void
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}
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declare i32 @llvm.umin.i32 (i32, i32)
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define void @umin_i32(i32 %n, i32* noalias %x, i32* noalias %y) {
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; CHECK-LABEL: @umin_i32(
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; CHECK: call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]])
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; CHECK: ret void
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %loop, label %end
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%xi = getelementptr inbounds i32, i32* %x, i32 %iv
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%yi = getelementptr inbounds i32, i32* %y, i32 %iv
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%xld = load i32, i32* %xi, align 4
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%yld = load i32, i32* %yi, align 4
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%call = tail call i32 @llvm.umin.i32(i32 %xld, i32 %yld)
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store i32 %call, i32* %xi, align 4
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%iv.next = add i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, %n
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br i1 %exitcond, label %end, label %loop
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end:
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ret void
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}
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declare i32 @llvm.umax.i32 (i32, i32)
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define void @umax_i32(i32 %n, i32* noalias %x, i32* noalias %y) {
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; CHECK-LABEL: @umax_i32(
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; CHECK: call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[WIDE_LOADX:%.*]], <4 x i32> [[WIDE_LOADY:%.*]])
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; CHECK: ret void
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %loop, label %end
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ]
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%xi = getelementptr inbounds i32, i32* %x, i32 %iv
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%yi = getelementptr inbounds i32, i32* %y, i32 %iv
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%xld = load i32, i32* %xi, align 4
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%yld = load i32, i32* %yi, align 4
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%call = tail call i32 @llvm.umax.i32(i32 %xld, i32 %yld)
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store i32 %call, i32* %xi, align 4
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%iv.next = add i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, %n
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br i1 %exitcond, label %end, label %loop
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end:
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ret void
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}
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declare i32 @llvm.fshl.i32 (i32, i32, i32)
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define void @fshl_i32(i32 %n, i32* noalias %x, i32* noalias %y, i32 %shAmt) {
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