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[PowerPC] Add a pattern for a runtime bit check

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Following a suggestion by Sanjay, we should lower:

  %shl = shl i32 1, %y
  %and = and i32 %x, %shl
  %cmp = icmp eq i32 %and, %shl
  ret i1 %cmp

into:

  subfic r4, r4, 32
  rlwnm r3, r3, r4, 31, 31

Add this pattern and some associated patterns for the 64-bit case and the
not-equal case. Fixes PR27356.

llvm-svn: 280454
This commit is contained in:
Hal Finkel 2016-09-02 02:34:44 +00:00
parent cde63257b5
commit 7d3268d25e
2 changed files with 94 additions and 0 deletions
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40
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -3185,6 +3185,46 @@ defm : ExtSetCCPat<SETLE,
OutPatFrag<(ops node:$in),
(RLDICL $in, 1, 63)> >;
// An extended SETCC with shift amount.
multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
OutPatFrag rfrag, OutPatFrag rfrag8> {
def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
(rfrag $s1, $sa)>;
def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
(rfrag8 $s1, $sa)>;
def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
(EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
(rfrag $s1, $sa)>;
def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
(rfrag8 $s1, $sa)>;
def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
(EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
}
defm : ExtSetCCShiftPat<SETNE,
PatFrag<(ops node:$in, node:$sa, node:$cc),
(setcc (and $in, (shl 1, $sa)), 0, $cc)>,
OutPatFrag<(ops node:$in, node:$sa),
(RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
OutPatFrag<(ops node:$in, node:$sa),
(RLDCL $in, (SUBFIC $sa, 64), 63)> >;
defm : ExtSetCCShiftPat<SETEQ,
PatFrag<(ops node:$in, node:$sa, node:$cc),
(setcc (and $in, (shl 1, $sa)), 0, $cc)>,
OutPatFrag<(ops node:$in, node:$sa),
(RLWNM (i32not $in),
(SUBFIC $sa, 32), 31, 31)>,
OutPatFrag<(ops node:$in, node:$sa),
(RLDCL (i64not $in),
(SUBFIC $sa, 64), 63)> >;
// SETCC for i32.
def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
(EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;

54
test/CodeGen/PowerPC/shift-cmp.ll Normal file
View File

@ -0,0 +1,54 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) {
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl
ret i1 %cmp
; CHECK-LABEL: @and_cmp_variable_power_of_two
; CHECK: subfic 4, 4, 32
; CHECK: rlwnm 3, 3, 4, 31, 31
; CHECK: blr
}
define i1 @and_cmp_variable_power_of_two_64(i64 %x, i64 %y) {
%shl = shl i64 1, %y
%and = and i64 %x, %shl
%cmp = icmp eq i64 %and, %shl
ret i1 %cmp
; CHECK-LABEL: @and_cmp_variable_power_of_two_64
; CHECK: subfic 4, 4, 64
; CHECK: rldcl 3, 3, 4, 63
; CHECK: blr
}
define i1 @and_ncmp_variable_power_of_two(i32 %x, i32 %y) {
%shl = shl i32 1, %y
%and = and i32 %x, %shl
%cmp = icmp ne i32 %and, %shl
ret i1 %cmp
; CHECK-LABEL: @and_ncmp_variable_power_of_two
; CHECK-DAG: subfic 4, 4, 32
; CHECK-DAG: nor [[REG:[0-9]+]], 3, 3
; CHECK: rlwnm 3, [[REG]], 4, 31, 31
; CHECK: blr
}
define i1 @and_ncmp_variable_power_of_two_64(i64 %x, i64 %y) {
%shl = shl i64 1, %y
%and = and i64 %x, %shl
%cmp = icmp ne i64 %and, %shl
ret i1 %cmp
; CHECK-LABEL: @and_ncmp_variable_power_of_two_64
; CHECK-DAG: subfic 4, 4, 64
; CHECK-DAG: not [[REG:[0-9]+]], 3
; CHECK: rldcl 3, [[REG]], 4, 63
; CHECK: blr
}