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[AArch64] [Windows] SEH opcodes should be scheduling boundaries.

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Prevents the post-RA scheduler from modifying the prologue sequences
emitting by frame lowering. This is roughly similar to what we do for
other targets: TargetInstrInfo::isSchedulingBoundary checks
isPosition(), which checks for CFI_INSTRUCTION.

isSEHInstruction is taken from D50288; it'll land with whatever patch
lands first.

Differential Revision: https://reviews.llvm.org/D53851

llvm-svn: 345634
This commit is contained in:
Eli Friedman 2018-10-30 19:24:51 +00:00
parent 38d898663d
commit 7d3a8434aa
9 changed files with 48 additions and 7 deletions
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34
lib/Target/AArch64/AArch64InstrInfo.cpp
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@ -1085,6 +1085,32 @@ bool AArch64InstrInfo::isFalkorShiftExtFast(const MachineInstr &MI) const {
}
}
bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) {
unsigned Opc = MI.getOpcode();
switch (Opc) {
default:
return false;
case AArch64::SEH_StackAlloc:
case AArch64::SEH_SaveFPLR:
case AArch64::SEH_SaveFPLR_X:
case AArch64::SEH_SaveReg:
case AArch64::SEH_SaveReg_X:
case AArch64::SEH_SaveRegP:
case AArch64::SEH_SaveRegP_X:
case AArch64::SEH_SaveFReg:
case AArch64::SEH_SaveFReg_X:
case AArch64::SEH_SaveFRegP:
case AArch64::SEH_SaveFRegP_X:
case AArch64::SEH_SetFP:
case AArch64::SEH_AddFP:
case AArch64::SEH_Nop:
case AArch64::SEH_PrologEnd:
case AArch64::SEH_EpilogStart:
case AArch64::SEH_EpilogEnd:
return true;
}
}
bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SubIdx) const {
@ -1137,6 +1163,14 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint(
return false;
}
bool AArch64InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const {
if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF))
return true;
return isSEHInstruction(MI);
}
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
/// Return true if the comparison instruction can be analyzed.

7
lib/Target/AArch64/AArch64InstrInfo.h
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@ -189,6 +189,10 @@ public:
unsigned FalseReg) const override;
void getNoop(MCInst &NopInst) const override;
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
/// Return true if the comparison instruction can be analyzed.
@ -262,6 +266,9 @@ public:
/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.
bool isFalkorShiftExtFast(const MachineInstr &MI) const;
/// Return true if the instructions is a SEH instruciton used for unwinding
/// on Windows.
static bool isSEHInstruction(const MachineInstr &MI);
private:
/// Sets the offsets on outlined instructions in \p MBB which use SP

2
test/CodeGen/AArch64/wineh1.mir
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@ -1,4 +1,4 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj -disable-post-ra \
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj \
# RUN: | llvm-readobj -unwind | FileCheck %s
# This test case checks the basic validity of the .xdata section. It's
# documented at:

2
test/CodeGen/AArch64/wineh2.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Test that the pre/post increment save of a flating point register is correct.
# CHECK: ExceptionData {

2
test/CodeGen/AArch64/wineh3.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Test that the register pairing of both general purpose and floating point
# registers is correctly saved in the .xdata section, as well as the pre/post
# increment of floating point register pairs.

2
test/CodeGen/AArch64/wineh4.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -disable-branch-fold -disable-post-ra -filetype=obj \
# RUN: -disable-branch-fold -filetype=obj \
# RUN: | llvm-readobj -unwind | FileCheck %s
# Check that multiple epilgoues are correctly placed in .xdata.

2
test/CodeGen/AArch64/wineh5.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check that that the large stack allocation is correctly represented in .xdata.

2
test/CodeGen/AArch64/wineh6.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -disable-post-ra -filetype=obj | llvm-readobj -unwind | FileCheck %s
# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check save_fplr_x, set_fp, alloc_s
# CHECK: ExceptionData {

2
test/CodeGen/AArch64/wineh7.mir
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@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
# RUN: -filetype=obj -disable-post-ra | llvm-readobj -unwind | FileCheck %s
# RUN: -filetype=obj | llvm-readobj -unwind | FileCheck %s
# Check AddFP
# CHECK: ExceptionData {