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[SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits

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An existing function Type::getScalarSizeInBits returns a uint64_t
instead of a TypeSize class because the caller is requesting a
scalar size, which cannot be scalable. This patch makes other
similar functions requesting a scalar size consistent with that,
thereby eliminating more than 1000 implicit TypeSize -> uint64_t
casts.

Differential revision: https://reviews.llvm.org/D87889
This commit is contained in:
David Sherwood 2020-09-18 08:39:31 +01:00
parent 7528ada67d
commit 7d764f4ed6
8 changed files with 15 additions and 16 deletions
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4
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -180,8 +180,8 @@ public:
return getValueType().getSizeInBits();
}
TypeSize getScalarValueSizeInBits() const {
return getValueType().getScalarType().getSizeInBits();
uint64_t getScalarValueSizeInBits() const {
return getValueType().getScalarType().getSizeInBits().getFixedSize();
}
// Forwarding methods - These forward to the corresponding methods in SDNode.

4
include/llvm/CodeGen/ValueTypes.h
View File

@ -318,8 +318,8 @@ namespace llvm {
return getExtendedSizeInBits();
}
TypeSize getScalarSizeInBits() const {
return getScalarType().getSizeInBits();
uint64_t getScalarSizeInBits() const {
return getScalarType().getSizeInBits().getFixedSize();
}
/// Return the number of bytes overwritten by a store of the specified value

4
include/llvm/Support/MachineValueType.h
View File

@ -923,8 +923,8 @@ namespace llvm {
}
}
TypeSize getScalarSizeInBits() const {
return getScalarType().getSizeInBits();
uint64_t getScalarSizeInBits() const {
return getScalarType().getSizeInBits().getFixedSize();
}
/// Return the number of bytes overwritten by a store of the specified value

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5300,9 +5300,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// of the BuildVec must mask the bottom bits of the extended element
// type
if (ConstantSDNode *Splat = BVec->getConstantSplatNode()) {
TypeSize ElementSize =
uint64_t ElementSize =
LoadVT.getVectorElementType().getScalarSizeInBits();
if (Splat->getAPIntValue().isMask((uint64_t)ElementSize)) {
if (Splat->getAPIntValue().isMask(ElementSize)) {
return DAG.getMaskedLoad(
ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(),
MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(),

4
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -5340,8 +5340,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
// amounts. This catches things like trying to shift an i1024 value by an
// i8, which is easy to fall into in generic code that uses
// TLI.getShiftAmount().
assert(N2.getValueType().getScalarSizeInBits().getFixedSize() >=
Log2_32_Ceil(VT.getScalarSizeInBits().getFixedSize()) &&
assert(N2.getValueType().getScalarSizeInBits() >=
Log2_32_Ceil(VT.getScalarSizeInBits()) &&
"Invalid use of small shift amount with oversized value!");
// Always fold shifts of i1 values so the code generator doesn't need to

5
lib/CodeGen/TargetLoweringBase.cpp
View File

@ -993,7 +993,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
NewVT = EltTy;
IntermediateVT = NewVT;
unsigned LaneSizeInBits = NewVT.getScalarSizeInBits().getFixedSize();
unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
// Convert sizes such as i33 to i64.
if (!isPowerOf2_32(LaneSizeInBits))
@ -1002,8 +1002,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
MVT DestVT = TLI->getRegisterType(NewVT);
RegisterVT = DestVT;
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
return NumVectorRegs *
(LaneSizeInBits / DestVT.getScalarSizeInBits().getFixedSize());
return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.

4
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7440,8 +7440,8 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
// trunc. So only std::min(SrcBits, DestBits) actually get defined in this
// segment.
EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
int BitsDefined =
std::min(OrigEltTy.getSizeInBits(), VT.getScalarSizeInBits());
int BitsDefined = std::min(OrigEltTy.getScalarSizeInBits(),
VT.getScalarSizeInBits());
int LanesDefined = BitsDefined / BitsPerShuffleLane;
// This source is expected to fill ResMultiplier lanes of the final shuffle,

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -7845,7 +7845,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
// trunc. So only std::min(SrcBits, DestBits) actually get defined in this
// segment.
EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
int BitsDefined = std::min(OrigEltTy.getScalarSizeInBits(),
VT.getScalarSizeInBits());
int LanesDefined = BitsDefined / BitsPerShuffleLane;