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32 to 64-bit zext pattern.

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llvm-svn: 146096
This commit is contained in:
Akira Hatanaka 2011-12-07 23:14:41 +00:00
parent dd3788b044
commit 7db0038ac0
2 changed files with 16 additions and 0 deletions
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5
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -222,6 +222,9 @@ def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
def DEXT : ExtBase<3, "dext", CPU64Regs>;
def DINS : InsBase<7, "dins", CPU64Regs>;
def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
"dsll32\t$rd, $rt, 0", [], IIAlu>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
@ -296,3 +299,5 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
def : Pat<(i32 (trunc CPU64Regs:$src)),
(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
// 32-to-64-bit extension
def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;

11
test/CodeGen/Mips/mips64ext.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
define i64 @zext64_32(i32 %a) nounwind readnone {
entry:
; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
; CHECK: dsrl32 ${{[0-9]+}}, $[[R1]], 0
%add = add i32 %a, 2
%conv = zext i32 %add to i64
ret i64 %conv
}