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Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. llvm-svn: 112416
This commit is contained in:
Bob Wilson
parent
9921d9c3c1
commit
807d004452
@ -73,10 +73,6 @@ let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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[LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_2Arg_Wide_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_3Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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@ -128,10 +124,6 @@ let Properties = [IntrNoMem, Commutative] in {
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def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
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def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
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def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
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def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
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def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
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// Vector Multiply.
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def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
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@ -172,10 +164,6 @@ def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
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def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
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def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
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def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
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def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
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def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
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// Vector Absolute Compare.
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let TargetPrefix = "arm" in {
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@ -1294,6 +1294,19 @@ class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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let isCommutable = Commutable;
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}
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// Long 3-register operations.
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class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
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bit Commutable>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
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OpcodeStr, Dt, "$dst, $src1, $src2", "",
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[(set QPR:$dst, (OpNode (TyQ (ExtOp (TyD DPR:$src1))),
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(TyQ (ExtOp (TyD DPR:$src2)))))]> {
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let isCommutable = Commutable;
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}
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// Long 3-register intrinsics.
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class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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@ -1325,14 +1338,15 @@ class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
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(OpTy (NEONvduplane (OpTy DPR_8:$src2),
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imm:$lane)))))]>;
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// Wide 3-register intrinsics.
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class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
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Intrinsic IntOp, bit Commutable>
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// Wide 3-register operations.
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class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
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SDNode OpNode, SDNode ExtOp, bit Commutable>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs QPR:$dst), (ins QPR:$src1, DPR:$src2), N3RegFrm, IIC_VSUBiD,
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OpcodeStr, Dt, "$dst, $src1, $src2", "",
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[(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
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[(set QPR:$dst, (OpNode (TyQ QPR:$src1),
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(TyQ (ExtOp (TyD DPR:$src2)))))]> {
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let isCommutable = Commutable;
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}
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@ -1684,6 +1698,23 @@ multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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}
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// Neon Long 3-register vector operations.
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multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin16, InstrItinClass itin32,
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string OpcodeStr, string Dt,
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SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
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def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
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OpcodeStr, !strconcat(Dt, "16"),
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v4i32, v4i16, OpNode, ExtOp, Commutable>;
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def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
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OpcodeStr, !strconcat(Dt, "32"),
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v2i64, v2i32, OpNode, ExtOp, Commutable>;
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def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
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OpcodeStr, !strconcat(Dt, "8"),
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v8i16, v8i8, OpNode, ExtOp, Commutable>;
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}
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// Neon Long 3-register vector intrinsics.
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// First with only element sizes of 16 and 32 bits:
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@ -1723,18 +1754,18 @@ multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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// Neon Wide 3-register vector intrinsics,
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// source operand element sizes of 8, 16 and 32 bits:
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multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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string OpcodeStr, string Dt,
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Intrinsic IntOp, bit Commutable = 0> {
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def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "8"),
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v8i16, v8i8, IntOp, Commutable>;
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def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "16"),
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v4i32, v4i16, IntOp, Commutable>;
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def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "32"),
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v2i64, v2i32, IntOp, Commutable>;
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multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
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string OpcodeStr, string Dt,
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SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
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def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "8"),
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v8i16, v8i8, OpNode, ExtOp, Commutable>;
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def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "16"),
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v4i32, v4i16, OpNode, ExtOp, Commutable>;
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def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
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OpcodeStr, !strconcat(Dt, "32"),
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v2i64, v2i32, OpNode, ExtOp, Commutable>;
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}
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@ -2073,13 +2104,13 @@ def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
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def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
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v4f32, v4f32, fadd, 1>;
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// VADDL : Vector Add Long (Q = D + D)
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defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
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"vaddl", "s", int_arm_neon_vaddls, 1>;
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defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
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"vaddl", "u", int_arm_neon_vaddlu, 1>;
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defm VADDLs : N3VL_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
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"vaddl", "s", add, sext, 1>;
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defm VADDLu : N3VL_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
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"vaddl", "u", add, zext, 1>;
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// VADDW : Vector Add Wide (Q = Q + D)
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defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw", "s", int_arm_neon_vaddws, 0>;
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defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw", "u", int_arm_neon_vaddwu, 0>;
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defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
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defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
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// VHADD : Vector Halving Add
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defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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@ -2324,13 +2355,13 @@ def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
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def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
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v4f32, v4f32, fsub, 0>;
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// VSUBL : Vector Subtract Long (Q = D - D)
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defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
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"vsubl", "s", int_arm_neon_vsubls, 1>;
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defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
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"vsubl", "u", int_arm_neon_vsublu, 1>;
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defm VSUBLs : N3VL_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
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"vsubl", "s", sub, sext, 0>;
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defm VSUBLu : N3VL_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
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"vsubl", "u", sub, zext, 0>;
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// VSUBW : Vector Subtract Wide (Q = Q - D)
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defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
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defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
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defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
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defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
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// VHSUB : Vector Halving Subtract
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defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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@ -2559,7 +2590,7 @@ def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
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defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabdl", "s", int_arm_neon_vabdls, 0>;
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defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabdl", "u", int_arm_neon_vabdlu, 0>;
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"vabdl", "u", int_arm_neon_vabdlu, 0>;
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// VABA : Vector Absolute Difference and Accumulate
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defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
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@ -79,8 +79,17 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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return true;
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}
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} else if (Name.compare(5, 9, "arm.neon.", 9) == 0) {
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if (Name.compare(14, 7, "vmovls.", 7) == 0 ||
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Name.compare(14, 7, "vmovlu.", 7) == 0) {
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if (((Name.compare(14, 5, "vmovl", 5) == 0 ||
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Name.compare(14, 5, "vaddl", 5) == 0 ||
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Name.compare(14, 5, "vsubl", 5) == 0) &&
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(Name.compare(19, 2, "s.", 2) == 0 ||
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Name.compare(19, 2, "u.", 2) == 0)) ||
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((Name.compare(14, 5, "vaddw", 5) == 0 ||
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Name.compare(14, 5, "vsubw", 5) == 0) &&
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(Name.compare(19, 2, "s.", 2) == 0 ||
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Name.compare(19, 2, "u.", 2) == 0))) {
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// Calls to these are transformed into IR without intrinsics.
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NewFn = 0;
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return true;
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@ -371,6 +380,27 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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} else if (Name.compare(14, 7, "vmovlu.", 7) == 0) {
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NewI = new ZExtInst(CI->getArgOperand(0), CI->getType(),
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"upgraded." + CI->getName(), CI);
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} else if (Name.compare(14, 4, "vadd", 4) == 0 ||
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Name.compare(14, 4, "vsub", 4) == 0) {
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// Extend one (vaddw/vsubw) or both (vaddl/vsubl) operands.
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Value *V0 = CI->getArgOperand(0);
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Value *V1 = CI->getArgOperand(1);
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if (Name.at(19) == 's') {
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if (Name.at(18) == 'l')
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V0 = new SExtInst(CI->getArgOperand(0), CI->getType(), "", CI);
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V1 = new SExtInst(CI->getArgOperand(1), CI->getType(), "", CI);
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} else {
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assert(Name.at(19) == 'u' && "unexpected vadd/vsub intrinsic");
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if (Name.at(18) == 'l')
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V0 = new ZExtInst(CI->getArgOperand(0), CI->getType(), "", CI);
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V1 = new ZExtInst(CI->getArgOperand(1), CI->getType(), "", CI);
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}
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if (Name.compare(14, 4, "vadd", 4) == 0)
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NewI = BinaryOperator::CreateAdd(V0, V1,"upgraded."+CI->getName(),CI);
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else
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NewI = BinaryOperator::CreateSub(V0, V1,"upgraded."+CI->getName(),CI);
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} else {
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llvm_unreachable("Unknown arm.neon function for CallInst upgrade.");
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}
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@ -28,6 +28,54 @@
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; CHECK-NOT: arm.neon.vmovlu.v2i64
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; CHECK: zext <2 x i32>
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; vaddl/vaddw should be auto-upgraded to add with sext/zext
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; CHECK: vaddls16
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; CHECK-NOT: arm.neon.vaddls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK-NEXT: sext <4 x i16>
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; CHECK-NEXT: add <4 x i32>
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; CHECK: vaddlu32
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; CHECK-NOT: arm.neon.vaddlu.v2i64
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; CHECK: zext <2 x i32>
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: add <2 x i64>
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; CHECK: vaddws8
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; CHECK-NOT: arm.neon.vaddws.v8i16
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; CHECK: sext <8 x i8>
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; CHECK-NEXT: add <8 x i16>
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; CHECK: vaddwu16
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; CHECK-NOT: arm.neon.vaddwu.v4i32
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; CHECK: zext <4 x i16>
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; CHECK-NEXT: add <4 x i32>
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; vsubl/vsubw should be auto-upgraded to sub with sext/zext
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; CHECK: vsubls16
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; CHECK-NOT: arm.neon.vsubls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK-NEXT: sext <4 x i16>
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; CHECK-NEXT: sub <4 x i32>
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; CHECK: vsublu32
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; CHECK-NOT: arm.neon.vsublu.v2i64
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; CHECK: zext <2 x i32>
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: sub <2 x i64>
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; CHECK: vsubws8
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; CHECK-NOT: arm.neon.vsubws.v8i16
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; CHECK: sext <8 x i8>
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; CHECK-NEXT: sub <8 x i16>
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; CHECK: vsubwu16
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; CHECK-NOT: arm.neon.vsubwu.v4i32
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; CHECK: zext <4 x i16>
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; CHECK-NEXT: sub <4 x i32>
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; vld* and vst* intrinsic calls need an alignment argument (defaulted to 1)
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; CHECK: vld1i8
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Binary file not shown.
@ -157,8 +157,10 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vaddl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i16> %tmp3
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%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
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%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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@ -166,8 +168,10 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vaddl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i32> %tmp3
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%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
|
||||
%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp5 = add <4 x i32> %tmp3, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -175,8 +179,10 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vaddl.s32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
|
||||
%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp5 = add <2 x i64> %tmp3, %tmp4
|
||||
ret <2 x i64> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
@ -184,8 +190,10 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vaddl.u8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
|
||||
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -193,8 +201,10 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vaddl.u16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
|
||||
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp5 = add <4 x i32> %tmp3, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -202,25 +212,20 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vaddl.u32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
|
||||
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp5 = add <2 x i64> %tmp3, %tmp4
|
||||
ret <2 x i64> %tmp5
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vaddws8:
|
||||
;CHECK: vaddw.s8
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp4 = add <8 x i16> %tmp1, %tmp3
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -228,8 +233,9 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vaddw.s16
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp4 = add <4 x i32> %tmp1, %tmp3
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -237,8 +243,9 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vaddw.s32
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp4 = add <2 x i64> %tmp1, %tmp3
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
@ -246,8 +253,9 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vaddw.u8
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp4 = add <8 x i16> %tmp1, %tmp3
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -255,8 +263,9 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vaddw.u16
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp4 = add <4 x i32> %tmp1, %tmp3
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -264,14 +273,7 @@ define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vaddw.u32
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp4 = add <2 x i64> %tmp1, %tmp3
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
|
||||
|
||||
@ -157,8 +157,10 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vsubl.s8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
|
||||
%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp5 = sub <8 x i16> %tmp3, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -166,8 +168,10 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vsubl.s16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
|
||||
%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp5 = sub <4 x i32> %tmp3, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -175,8 +179,10 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vsubl.s32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
|
||||
%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp5 = sub <2 x i64> %tmp3, %tmp4
|
||||
ret <2 x i64> %tmp5
|
||||
}
|
||||
|
||||
define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
@ -184,8 +190,10 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vsubl.u8
|
||||
%tmp1 = load <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
|
||||
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp5 = sub <8 x i16> %tmp3, %tmp4
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -193,8 +201,10 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vsubl.u16
|
||||
%tmp1 = load <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
|
||||
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp5 = sub <4 x i32> %tmp3, %tmp4
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -202,25 +212,20 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vsubl.u32
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
|
||||
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp5 = sub <2 x i64> %tmp3, %tmp4
|
||||
ret <2 x i64> %tmp5
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vsubws8:
|
||||
;CHECK: vsubw.s8
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp4 = sub <8 x i16> %tmp1, %tmp3
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -228,8 +233,9 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vsubw.s16
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp4 = sub <4 x i32> %tmp1, %tmp3
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -237,8 +243,9 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vsubw.s32
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp4 = sub <2 x i64> %tmp1, %tmp3
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
@ -246,8 +253,9 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vsubw.u8
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i8>* %B
|
||||
%tmp3 = call <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
|
||||
ret <8 x i16> %tmp3
|
||||
%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
|
||||
%tmp4 = sub <8 x i16> %tmp1, %tmp3
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
@ -255,8 +263,9 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK: vsubw.u16
|
||||
%tmp1 = load <4 x i32>* %A
|
||||
%tmp2 = load <4 x i16>* %B
|
||||
%tmp3 = call <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
|
||||
ret <4 x i32> %tmp3
|
||||
%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
|
||||
%tmp4 = sub <4 x i32> %tmp1, %tmp3
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
@ -264,14 +273,7 @@ define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK: vsubw.u32
|
||||
%tmp1 = load <2 x i64>* %A
|
||||
%tmp2 = load <2 x i32>* %B
|
||||
%tmp3 = call <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
|
||||
ret <2 x i64> %tmp3
|
||||
%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
|
||||
%tmp4 = sub <2 x i64> %tmp1, %tmp3
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
|
||||
|
||||
declare <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
|
||||
declare <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
|
||||
declare <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
|
||||
|
||||
Loading…
Reference in New Issue
Block a user