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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
llvm-svn: 224868
This commit is contained in:
Colin LeMahieu
parent
510942bba6
commit
80ca4bde69
@ -595,17 +595,17 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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TM.getSubtargetImpl()->getInstrInfo());
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if (LoadedVT == MVT::i64) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::POST_LDrid;
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Opcode = Hexagon::L2_loadrd_pi;
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else
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Opcode = Hexagon::L2_loadrd_io;
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} else if (LoadedVT == MVT::i32) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::POST_LDriw;
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Opcode = Hexagon::L2_loadri_pi;
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else
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Opcode = Hexagon::L2_loadri_io;
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} else if (LoadedVT == MVT::i16) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
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Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
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else
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Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
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} else if (LoadedVT == MVT::i8) {
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@ -684,14 +684,14 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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case Hexagon::L2_loadrub_io:
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return isUInt<6>(MI->getOperand(2).getImm());
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case Hexagon::POST_LDrid:
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case Hexagon::L2_loadrd_pi:
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return isShiftedInt<4,3>(MI->getOperand(3).getImm());
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case Hexagon::POST_LDriw:
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case Hexagon::L2_loadri_pi:
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return isShiftedInt<4,2>(MI->getOperand(3).getImm());
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case Hexagon::POST_LDrih:
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case Hexagon::POST_LDriuh:
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case Hexagon::L2_loadrh_pi:
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case Hexagon::L2_loadruh_pi:
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return isShiftedInt<4,1>(MI->getOperand(3).getImm());
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case Hexagon::L2_loadrb_pi:
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@ -1357,16 +1357,16 @@ isConditionalLoad (const MachineInstr* MI) const {
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case Hexagon::L2_ploadrubt_io:
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case Hexagon::L2_ploadrubf_io:
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return true;
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case Hexagon::POST_LDrid_cPt :
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case Hexagon::POST_LDrid_cNotPt :
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case Hexagon::POST_LDriw_cPt :
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case Hexagon::POST_LDriw_cNotPt :
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case Hexagon::POST_LDrih_cPt :
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case Hexagon::POST_LDrih_cNotPt :
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case Hexagon::L2_ploadrdt_pi :
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case Hexagon::L2_ploadrdf_pi :
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case Hexagon::L2_ploadrit_pi :
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case Hexagon::L2_ploadrif_pi :
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case Hexagon::L2_ploadrht_pi :
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case Hexagon::L2_ploadrhf_pi :
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case Hexagon::L2_ploadrbt_pi :
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case Hexagon::L2_ploadrbf_pi :
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case Hexagon::POST_LDriuh_cPt :
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case Hexagon::POST_LDriuh_cNotPt :
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case Hexagon::L2_ploadruht_pi :
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case Hexagon::L2_ploadruhf_pi :
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case Hexagon::L2_ploadrubt_pi :
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case Hexagon::L2_ploadrubf_pi :
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return QRI.Subtarget.hasV4TOps();
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@ -1701,55 +1701,19 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in {
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defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
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}
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multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2++#$offset)",
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[],
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"$src2 = $dst2">;
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// post increment halfword loads with immediate offset
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let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
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defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
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defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
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}
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multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
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Operand ImmOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
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// Predicate new
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let Predicates = [HasV4T], validSubTargets = HasV4SubT in
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defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
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}
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}
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// post increment word loads with immediate offset
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let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
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defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
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multiclass LD_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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let BaseOpcode = "POST_"#BaseOp in {
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let isPredicable = 1 in
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def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
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(ins IntRegs:$src1, ImmOp:$offset),
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"$dst = "#mnemonic#"($src1++#$offset)",
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[],
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"$src1 = $dst2">;
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let isPredicated = 1 in {
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defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
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defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
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}
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}
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}
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let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
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defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>,
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PredNewRel;
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defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>,
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PredNewRel;
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defm POST_LDriw : LD_PostInc2<"memw", "LDriw", IntRegs, s4_2Imm>,
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PredNewRel;
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defm POST_LDrid : LD_PostInc2<"memd", "LDrid", DoubleRegs, s4_3Imm>,
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PredNewRel;
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}
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// post increment doubleword loads with immediate offset
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let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
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defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
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def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
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(i32 (L2_loadrb_io AddrFI:$addr, 0)) >;
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@ -2,6 +2,8 @@
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0x70 0xd8 0xd5 0x41
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# CHECK: if (p3) r17:16 = memd(r21 + #24)
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0xb0 0xc0 0xd5 0x9b
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# CHECK: r17:16 = memd(r21++#40)
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0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24)
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@ -10,6 +12,16 @@
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0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24)
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0xb0 0xe6 0xd5 0x9b
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# CHECK: if (p3) r17:16 = memd(r21++#40)
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0xb0 0xee 0xd5 0x9b
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# CHECK: if (!p3) r17:16 = memd(r21++#40)
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0x03 0x40 0x45 0x85 0xb0 0xf6 0xd5 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17:16 = memd(r21++#40)
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0x03 0x40 0x45 0x85 0xb0 0xfe 0xd5 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40)
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0xf1 0xc3 0x15 0x91
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# CHECK: r17 = memb(r21 + #31)
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@ -38,6 +50,18 @@
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0xf1 0xc3 0x55 0x91
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# CHECK: r17 = memh(r21 + #62)
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0xb1 0xc0 0x55 0x9b
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# CHECK: r17 = memh(r21++#10)
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0xb1 0xe6 0x55 0x9b
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# CHECK: if (p3) r17 = memh(r21++#10)
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0xb1 0xee 0x55 0x9b
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# CHECK: if (!p3) r17 = memh(r21++#10)
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0x03 0x40 0x45 0x85 0xb1 0xf6 0x55 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17 = memh(r21++#10)
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0x03 0x40 0x45 0x85 0xb1 0xfe 0x55 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
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0xf1 0xc3 0x35 0x91
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# CHECK: r17 = memub(r21 + #31)
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@ -66,6 +90,8 @@
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0xb1 0xc2 0x75 0x91
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# CHECK: r17 = memuh(r21 + #42)
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0xb1 0xc0 0x75 0x9b
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# CHECK: r17 = memuh(r21++#10)
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0xb1 0xda 0x75 0x41
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# CHECK: if (p3) r17 = memuh(r21 + #42)
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0xb1 0xda 0x75 0x45
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@ -76,6 +102,16 @@
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0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)
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0xb1 0xe6 0x75 0x9b
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# CHECK: if (p3) r17 = memuh(r21++#10)
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0xb1 0xee 0x75 0x9b
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# CHECK: if (!p3) r17 = memuh(r21++#10)
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0x03 0x40 0x45 0x85 0xb1 0xf6 0x75 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17 = memuh(r21++#10)
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0x03 0x40 0x45 0x85 0xb1 0xfe 0x75 0x9b
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10)
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0xb1 0xc2 0x95 0x91
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# CHECK: r17 = memw(r21 + #84)
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