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RegAllocFast: Further cleanups; NFC
llvm-svn: 346576
This commit is contained in:
Matthias Braun
parent
9a582fbd2d
commit
81c3de0935
@ -177,6 +177,8 @@ namespace {
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bool runOnMachineFunction(MachineFunction &MF) override;
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void allocateBasicBlock(MachineBasicBlock &MBB);
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void allocateInstruction(MachineInstr &MI);
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void handleDebugValue(MachineInstr &MI);
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void handleThroughOperands(MachineInstr &MI,
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SmallVectorImpl<unsigned> &VirtDead);
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bool isLastUseOfLocalReg(const MachineOperand &MO) const;
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@ -207,7 +209,7 @@ namespace {
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LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg,
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unsigned Hint);
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void spillAll(MachineBasicBlock::iterator MI);
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bool setPhysReg(MachineInstr &MI, unsigned OpNum, MCPhysReg PhysReg);
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bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
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int getStackSpaceFor(unsigned VirtReg);
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void spill(MachineBasicBlock::iterator Before, unsigned VirtReg,
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@ -373,7 +375,8 @@ void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, LiveReg &LR) {
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/// Spill all dirty virtregs without killing them.
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void RegAllocFast::spillAll(MachineBasicBlock::iterator MI) {
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if (LiveVirtRegs.empty()) return;
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if (LiveVirtRegs.empty())
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return;
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// The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
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// of spilling here is deterministic, if arbitrary.
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for (LiveReg &LR : LiveVirtRegs) {
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@ -490,9 +493,9 @@ void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI,
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}
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}
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/// Return the cost of spilling clearing out PhysReg and aliases so it is
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/// free for allocation. Returns 0 when PhysReg is free or disabled with all
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/// aliases disabled - it can be allocated directly.
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/// Return the cost of spilling clearing out PhysReg and aliases so it is free
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/// for allocation. Returns 0 when PhysReg is free or disabled with all aliases
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/// disabled - it can be allocated directly.
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/// \returns spillImpossible when PhysReg or an alias can't be spilled.
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unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
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if (isRegUsedInInstr(PhysReg)) {
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@ -588,16 +591,13 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint) {
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}
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}
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LLVM_DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from "
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<< TRI->getRegClassName(&RC) << '\n');
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unsigned BestReg = 0;
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MCPhysReg BestReg = 0;
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unsigned BestCost = spillImpossible;
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for (MCPhysReg PhysReg : AllocationOrder) {
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LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
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unsigned Cost = calcSpillCost(PhysReg);
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LLVM_DEBUG(dbgs() << "Cost: " << Cost << " BestCost: " << BestCost << '\n');
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// Cost is 0 when all aliases are already disabled.
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// Immediate take a register with cost 0.
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if (Cost == 0) {
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assignVirtToPhysReg(LR, PhysReg);
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return;
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@ -609,7 +609,8 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint) {
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}
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if (!BestReg) {
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// Nothing we can do. Report an error and keep going with a bad allocation.
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// Nothing we can do: Report an error and keep going with an invalid
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// allocation.
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if (MI.isInlineAsm())
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MI.emitError("inline assembly requires more registers than available");
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else
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@ -704,9 +705,8 @@ RegAllocFast::LiveReg &RegAllocFast::reloadVirtReg(MachineInstr &MI,
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/// Changes operand OpNum in MI the refer the PhysReg, considering subregs. This
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/// may invalidate any operand pointers. Return true if the operand kills its
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/// register.
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bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum,
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bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO,
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MCPhysReg PhysReg) {
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MachineOperand &MO = MI.getOperand(OpNum);
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bool Dead = MO.isDead();
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if (!MO.getSubReg()) {
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MO.setReg(PhysReg);
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@ -769,7 +769,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI,
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SmallVector<unsigned, 8> PartialDefs;
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LLVM_DEBUG(dbgs() << "Allocating tied uses.\n");
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for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI.getOperand(I);
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MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
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@ -780,7 +780,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI,
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<< ".\n");
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LiveReg &LR = reloadVirtReg(MI, I, Reg, 0);
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MCPhysReg PhysReg = LR.PhysReg;
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setPhysReg(MI, I, PhysReg);
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setPhysReg(MI, MO, PhysReg);
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// Note: we don't update the def operand yet. That would cause the normal
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// def-scan to attempt spilling.
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} else if (MO.getSubReg() && MI.readsVirtualRegister(Reg)) {
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@ -802,7 +802,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI,
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continue;
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// Note: defineVirtReg may invalidate MO.
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MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, 0);
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if (setPhysReg(MI, I, PhysReg))
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if (setPhysReg(MI, MI.getOperand(I), PhysReg))
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VirtDead.push_back(Reg);
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}
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@ -860,6 +860,199 @@ void RegAllocFast::dumpState() {
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}
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#endif
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void RegAllocFast::allocateInstruction(MachineInstr &MI) {
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const MCInstrDesc &MCID = MI.getDesc();
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// If this is a copy, we may be able to coalesce.
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unsigned CopySrcReg = 0;
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unsigned CopyDstReg = 0;
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unsigned CopySrcSub = 0;
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unsigned CopyDstSub = 0;
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if (MI.isCopy()) {
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CopyDstReg = MI.getOperand(0).getReg();
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CopySrcReg = MI.getOperand(1).getReg();
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CopyDstSub = MI.getOperand(0).getSubReg();
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CopySrcSub = MI.getOperand(1).getSubReg();
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}
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// Track registers used by instruction.
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UsedInInstr.clear();
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// First scan.
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// Mark physreg uses and early clobbers as used.
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// Find the end of the virtreg operands
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unsigned VirtOpEnd = 0;
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bool hasTiedOps = false;
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bool hasEarlyClobbers = false;
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bool hasPartialRedefs = false;
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bool hasPhysDefs = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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// Make sure MRI knows about registers clobbered by regmasks.
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if (MO.isRegMask()) {
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MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
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continue;
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}
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!Reg) continue;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VirtOpEnd = i+1;
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if (MO.isUse()) {
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hasTiedOps = hasTiedOps ||
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MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
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} else {
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if (MO.isEarlyClobber())
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hasEarlyClobbers = true;
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if (MO.getSubReg() && MI.readsVirtualRegister(Reg))
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hasPartialRedefs = true;
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}
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continue;
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}
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if (!MRI->isAllocatable(Reg)) continue;
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if (MO.isUse()) {
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usePhysReg(MO);
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} else if (MO.isEarlyClobber()) {
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definePhysReg(MI, Reg,
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(MO.isImplicit() || MO.isDead()) ? regFree : regReserved);
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hasEarlyClobbers = true;
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} else
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hasPhysDefs = true;
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}
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// The instruction may have virtual register operands that must be allocated
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// the same register at use-time and def-time: early clobbers and tied
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// operands. If there are also physical defs, these registers must avoid
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// both physical defs and uses, making them more constrained than normal
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// operands.
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// Similarly, if there are multiple defs and tied operands, we must make
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// sure the same register is allocated to uses and defs.
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// We didn't detect inline asm tied operands above, so just make this extra
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// pass for all inline asm.
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if (MI.isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
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(hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
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handleThroughOperands(MI, VirtDead);
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// Don't attempt coalescing when we have funny stuff going on.
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CopyDstReg = 0;
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// Pretend we have early clobbers so the use operands get marked below.
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// This is not necessary for the common case of a single tied use.
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hasEarlyClobbers = true;
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}
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// Second scan.
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// Allocate virtreg uses.
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for (unsigned I = 0; I != VirtOpEnd; ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
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if (MO.isUse()) {
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LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg);
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MCPhysReg PhysReg = LR.PhysReg;
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CopySrcReg = (CopySrcReg == Reg || CopySrcReg == PhysReg) ? PhysReg : 0;
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if (setPhysReg(MI, MO, PhysReg))
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killVirtReg(LR);
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}
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}
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// Track registers defined by instruction - early clobbers and tied uses at
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// this point.
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UsedInInstr.clear();
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if (hasEarlyClobbers) {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
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// Look for physreg defs and tied uses.
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if (!MO.isDef() && !MO.isTied()) continue;
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markRegUsedInInstr(Reg);
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}
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}
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unsigned DefOpEnd = MI.getNumOperands();
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if (MI.isCall()) {
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// Spill all virtregs before a call. This serves one purpose: If an
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// exception is thrown, the landing pad is going to expect to find
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// registers in their spill slots.
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// Note: although this is appealing to just consider all definitions
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// as call-clobbered, this is not correct because some of those
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// definitions may be used later on and we do not want to reuse
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// those for virtual registers in between.
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LLVM_DEBUG(dbgs() << " Spilling remaining registers before call.\n");
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spillAll(MI);
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}
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// Third scan.
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// Allocate defs and collect dead defs.
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for (unsigned I = 0; I != DefOpEnd; ++I) {
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const MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (!MRI->isAllocatable(Reg)) continue;
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definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
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continue;
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}
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MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg);
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if (setPhysReg(MI, MI.getOperand(I), PhysReg)) {
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VirtDead.push_back(Reg);
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CopyDstReg = 0; // cancel coalescing;
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} else
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CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0;
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}
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// Kill dead defs after the scan to ensure that multiple defs of the same
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// register are allocated identically. We didn't need to do this for uses
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// because we are crerating our own kill flags, and they are always at the
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// last use.
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for (unsigned VirtReg : VirtDead)
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killVirtReg(VirtReg);
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VirtDead.clear();
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LLVM_DEBUG(dbgs() << "<< " << MI);
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if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) {
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LLVM_DEBUG(dbgs() << "Mark identity copy for removal\n");
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Coalesced.push_back(&MI);
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}
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}
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void RegAllocFast::handleDebugValue(MachineInstr &MI) {
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MachineOperand &MO = MI.getOperand(0);
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// Ignore DBG_VALUEs that aren't based on virtual registers. These are
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// mostly constants and frame indices.
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if (!MO.isReg())
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return;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return;
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// See if this virtual register has already been allocated to a physical
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// register or spilled to a stack slot.
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LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
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if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
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setPhysReg(MI, MO, LRI->PhysReg);
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} else {
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int SS = StackSlotForVirtReg[Reg];
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if (SS != -1) {
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// Modify DBG_VALUE now that the value is in a spill slot.
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updateDbgValueForSpill(MI, SS);
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LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << MI);
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return;
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}
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// We can't allocate a physreg for a DebugValue, sorry!
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LLVM_DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
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MO.setReg(0);
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}
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// If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so
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// that future spills of Reg will have DBG_VALUEs.
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LiveDbgValueMap[Reg].push_back(&MI);
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}
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void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
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this->MBB = &MBB;
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LLVM_DEBUG(dbgs() << "\nAllocating " << MBB);
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@ -879,205 +1072,19 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
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// Otherwise, sequentially allocate each instruction in the MBB.
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for (MachineInstr &MI : MBB) {
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const MCInstrDesc &MCID = MI.getDesc();
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LLVM_DEBUG(dbgs() << "\n>> " << MI << "Regs:"; dumpState());
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LLVM_DEBUG(
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dbgs() << "\n>> " << MI << "Regs:";
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dumpState()
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);
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// Debug values are not allowed to change codegen in any way.
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// Special handling for debug values. Note that they are not allowed to
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// affect codegen of the other instructions in any way.
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if (MI.isDebugValue()) {
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MachineInstr *DebugMI = &MI;
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MachineOperand &MO = DebugMI->getOperand(0);
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// Ignore DBG_VALUEs that aren't based on virtual registers. These are
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// mostly constants and frame indices.
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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// See if this virtual register has already been allocated to a physical
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// register or spilled to a stack slot.
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LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
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if (LRI != LiveVirtRegs.end() && LRI->PhysReg)
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setPhysReg(*DebugMI, 0, LRI->PhysReg);
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else {
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int SS = StackSlotForVirtReg[Reg];
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if (SS != -1) {
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// Modify DBG_VALUE now that the value is in a spill slot.
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updateDbgValueForSpill(*DebugMI, SS);
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LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:"
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<< "\t" << *DebugMI);
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continue;
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}
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// We can't allocate a physreg for a DebugValue, sorry!
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LLVM_DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
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MO.setReg(0);
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}
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// If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so
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// that future spills of Reg will have DBG_VALUEs.
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LiveDbgValueMap[Reg].push_back(DebugMI);
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handleDebugValue(MI);
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continue;
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}
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if (MI.isDebugLabel())
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continue;
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// If this is a copy, we may be able to coalesce.
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unsigned CopySrcReg = 0;
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unsigned CopyDstReg = 0;
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unsigned CopySrcSub = 0;
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unsigned CopyDstSub = 0;
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if (MI.isCopy()) {
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CopyDstReg = MI.getOperand(0).getReg();
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CopySrcReg = MI.getOperand(1).getReg();
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CopyDstSub = MI.getOperand(0).getSubReg();
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CopySrcSub = MI.getOperand(1).getSubReg();
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}
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// Track registers used by instruction.
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UsedInInstr.clear();
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// First scan.
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// Mark physreg uses and early clobbers as used.
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// Find the end of the virtreg operands
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unsigned VirtOpEnd = 0;
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bool hasTiedOps = false;
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bool hasEarlyClobbers = false;
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bool hasPartialRedefs = false;
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bool hasPhysDefs = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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// Make sure MRI knows about registers clobbered by regmasks.
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if (MO.isRegMask()) {
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MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
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continue;
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}
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!Reg) continue;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VirtOpEnd = i+1;
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if (MO.isUse()) {
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hasTiedOps = hasTiedOps ||
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MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
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} else {
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if (MO.isEarlyClobber())
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hasEarlyClobbers = true;
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if (MO.getSubReg() && MI.readsVirtualRegister(Reg))
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hasPartialRedefs = true;
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}
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continue;
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}
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if (!MRI->isAllocatable(Reg)) continue;
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if (MO.isUse()) {
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usePhysReg(MO);
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} else if (MO.isEarlyClobber()) {
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definePhysReg(MI, Reg,
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(MO.isImplicit() || MO.isDead()) ? regFree : regReserved);
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hasEarlyClobbers = true;
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} else
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hasPhysDefs = true;
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}
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// The instruction may have virtual register operands that must be allocated
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// the same register at use-time and def-time: early clobbers and tied
|
||||
// operands. If there are also physical defs, these registers must avoid
|
||||
// both physical defs and uses, making them more constrained than normal
|
||||
// operands.
|
||||
// Similarly, if there are multiple defs and tied operands, we must make
|
||||
// sure the same register is allocated to uses and defs.
|
||||
// We didn't detect inline asm tied operands above, so just make this extra
|
||||
// pass for all inline asm.
|
||||
if (MI.isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
|
||||
(hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
|
||||
handleThroughOperands(MI, VirtDead);
|
||||
// Don't attempt coalescing when we have funny stuff going on.
|
||||
CopyDstReg = 0;
|
||||
// Pretend we have early clobbers so the use operands get marked below.
|
||||
// This is not necessary for the common case of a single tied use.
|
||||
hasEarlyClobbers = true;
|
||||
}
|
||||
|
||||
// Second scan.
|
||||
// Allocate virtreg uses.
|
||||
for (unsigned I = 0; I != VirtOpEnd; ++I) {
|
||||
const MachineOperand &MO = MI.getOperand(I);
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
||||
if (MO.isUse()) {
|
||||
LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg);
|
||||
MCPhysReg PhysReg = LR.PhysReg;
|
||||
CopySrcReg = (CopySrcReg == Reg || CopySrcReg == PhysReg) ? PhysReg : 0;
|
||||
if (setPhysReg(MI, I, PhysReg))
|
||||
killVirtReg(LR);
|
||||
}
|
||||
}
|
||||
|
||||
// Track registers defined by instruction - early clobbers and tied uses at
|
||||
// this point.
|
||||
UsedInInstr.clear();
|
||||
if (hasEarlyClobbers) {
|
||||
for (const MachineOperand &MO : MI.operands()) {
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
||||
// Look for physreg defs and tied uses.
|
||||
if (!MO.isDef() && !MO.isTied()) continue;
|
||||
markRegUsedInInstr(Reg);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned DefOpEnd = MI.getNumOperands();
|
||||
if (MI.isCall()) {
|
||||
// Spill all virtregs before a call. This serves one purpose: If an
|
||||
// exception is thrown, the landing pad is going to expect to find
|
||||
// registers in their spill slots.
|
||||
// Note: although this is appealing to just consider all definitions
|
||||
// as call-clobbered, this is not correct because some of those
|
||||
// definitions may be used later on and we do not want to reuse
|
||||
// those for virtual registers in between.
|
||||
LLVM_DEBUG(dbgs() << " Spilling remaining registers before call.\n");
|
||||
spillAll(MI);
|
||||
}
|
||||
|
||||
// Third scan.
|
||||
// Allocate defs and collect dead defs.
|
||||
for (unsigned I = 0; I != DefOpEnd; ++I) {
|
||||
const MachineOperand &MO = MI.getOperand(I);
|
||||
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
|
||||
continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
|
||||
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
||||
if (!MRI->isAllocatable(Reg)) continue;
|
||||
definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
|
||||
continue;
|
||||
}
|
||||
MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg);
|
||||
if (setPhysReg(MI, I, PhysReg)) {
|
||||
VirtDead.push_back(Reg);
|
||||
CopyDstReg = 0; // cancel coalescing;
|
||||
} else
|
||||
CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0;
|
||||
}
|
||||
|
||||
// Kill dead defs after the scan to ensure that multiple defs of the same
|
||||
// register are allocated identically. We didn't need to do this for uses
|
||||
// because we are crerating our own kill flags, and they are always at the
|
||||
// last use.
|
||||
for (unsigned VirtReg : VirtDead)
|
||||
killVirtReg(VirtReg);
|
||||
VirtDead.clear();
|
||||
|
||||
if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) {
|
||||
LLVM_DEBUG(dbgs() << "-- coalescing: " << MI);
|
||||
Coalesced.push_back(&MI);
|
||||
} else {
|
||||
LLVM_DEBUG(dbgs() << "<< " << MI);
|
||||
}
|
||||
allocateInstruction(MI);
|
||||
}
|
||||
|
||||
// Spill all physical registers holding virtual registers now.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user