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Add 128-bit pmovmskb intrinsic support.
llvm-svn: 27255
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@ -298,4 +298,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_v8i16_ty], [InstrNoMem]>;
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def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
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Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
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Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
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}
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@ -686,13 +686,6 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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MOVHLPS_shuffle_mask)))]>;
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}
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def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskps {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
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def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskpd {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
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// Conversion instructions
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def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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@ -1374,6 +1367,18 @@ def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
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// Miscellaneous Instructions
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//===----------------------------------------------------------------------===//
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// Mask creation
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def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskps {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
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def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"movmskpd {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
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def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"pmovmskb {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
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// Prefetching loads
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def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
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"prefetcht0 $src", []>, TB,
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