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https://github.com/RPCS3/llvm-mirror.git
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Remove hard coded registers in ARM ldrexd and strexd instructions
This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
This commit is contained in:
Weiming Zhao
parent
a66c9f2861
commit
85dce59506
@ -266,6 +266,7 @@ private:
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std::vector<SDValue> &OutOps);
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// Form pairs of consecutive S, D, or Q registers.
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SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
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SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
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SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
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SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
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@ -1444,6 +1445,17 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
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return NULL;
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}
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/// \brief Form a GPRPair pseudo register from a pair of GPR regs.
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SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass =
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CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
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}
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/// PairSRegs - Form a D register from a pair of S registers.
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///
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SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
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@ -3009,17 +3021,19 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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SDValue Chain = N->getOperand(0);
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unsigned NewOpc = ARM::LDREXD;
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if (Subtarget->isThumb() && Subtarget->hasThumb2())
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NewOpc = ARM::t2LDREXD;
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bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
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unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
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// arm_ldrexd returns a i64 value in {i32, i32}
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std::vector<EVT> ResTys;
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ResTys.push_back(MVT::i32);
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ResTys.push_back(MVT::i32);
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if (isThumb) {
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ResTys.push_back(MVT::i32);
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ResTys.push_back(MVT::i32);
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} else
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ResTys.push_back(MVT::Untyped);
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ResTys.push_back(MVT::Other);
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// place arguments in the right order
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// Place arguments in the right order.
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SmallVector<SDValue, 7> Ops;
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Ops.push_back(MemAddr);
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Ops.push_back(getAL(CurDAG));
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@ -3032,30 +3046,35 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
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cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
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// Until there's support for specifing explicit register constraints
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// like the use of even/odd register pair, hardcode ldrexd to always
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// use the pair [R0, R1] to hold the load result.
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Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
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SDValue(Ld, 0), SDValue(0,0));
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Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
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SDValue(Ld, 1), Chain.getValue(1));
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// Remap uses.
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SDValue Glue = Chain.getValue(1);
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SDValue Glue = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
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if (!SDValue(N, 0).use_empty()) {
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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ARM::R0, MVT::i32, Glue);
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Glue = Result.getValue(2);
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SDValue Result;
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if (isThumb)
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Result = SDValue(Ld, 0);
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else {
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SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
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SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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dl, MVT::i32, MVT::Glue, SDValue(Ld, 0), SubRegIdx, Glue);
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Result = SDValue(ResNode,0);
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Glue = Result.getValue(1);
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}
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ReplaceUses(SDValue(N, 0), Result);
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}
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if (!SDValue(N, 1).use_empty()) {
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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ARM::R1, MVT::i32, Glue);
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Glue = Result.getValue(2);
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SDValue Result;
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if (isThumb)
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Result = SDValue(Ld, 1);
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else {
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SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
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SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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dl, MVT::i32, MVT::Glue, SDValue(Ld, 0), SubRegIdx, Glue);
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Result = SDValue(ResNode,0);
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Glue = Result.getValue(1);
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}
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ReplaceUses(SDValue(N, 1), Result);
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}
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ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
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ReplaceUses(SDValue(N, 2), Glue);
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return NULL;
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}
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@ -3066,38 +3085,27 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDValue Val1 = N->getOperand(3);
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SDValue MemAddr = N->getOperand(4);
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// Until there's support for specifing explicit register constraints
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// like the use of even/odd register pair, hardcode strexd to always
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// use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
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Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
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SDValue(0, 0));
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Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
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SDValue Glue = Chain.getValue(1);
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Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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ARM::R2, MVT::i32, Glue);
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Glue = Val0.getValue(1);
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Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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ARM::R3, MVT::i32, Glue);
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// Store exclusive double return a i32 value which is the return status
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// of the issued store.
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std::vector<EVT> ResTys;
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ResTys.push_back(MVT::i32);
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ResTys.push_back(MVT::Other);
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// place arguments in the right order
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bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
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// Place arguments in the right order.
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SmallVector<SDValue, 7> Ops;
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Ops.push_back(Val0);
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Ops.push_back(Val1);
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if (isThumb) {
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Ops.push_back(Val0);
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Ops.push_back(Val1);
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} else
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// arm_strexd uses GPRPair.
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Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
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Ops.push_back(MemAddr);
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Ops.push_back(getAL(CurDAG));
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Ops.push_back(CurDAG->getRegister(0, MVT::i32));
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Ops.push_back(Chain);
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unsigned NewOpc = ARM::STREXD;
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if (Subtarget->isThumb() && Subtarget->hasThumb2())
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NewOpc = ARM::t2STREXD;
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unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
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SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
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Ops.size());
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@ -5807,12 +5807,16 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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// for ldrexd must be different.
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BB = loopMBB;
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// Load
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unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned GPRPair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
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.addReg(ARM::R2, RegState::Define)
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.addReg(ARM::R3, RegState::Define).addReg(ptr));
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.addReg(GPRPair0, RegState::Define).addReg(ptr));
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// Copy r2/r3 into dest. (This copy will normally be coalesced.)
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
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.addReg(GPRPair0, 0, ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
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.addReg(GPRPair0, 0, ARM::gsub_1);
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if (IsCmpxchg) {
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// Add early exit
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@ -5831,24 +5835,56 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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// Copy to physregs for strexd
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unsigned setlo = MI->getOperand(5).getReg();
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unsigned sethi = MI->getOperand(6).getReg();
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
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unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(undef)
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.addReg(setlo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(sethi)
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.addImm(ARM::gsub_1);
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} else if (Op1) {
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// Perform binary operation
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
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unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), tmpRegLo)
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.addReg(destlo).addReg(vallo))
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.addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
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unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
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.addReg(desthi).addReg(valhi)).addReg(0);
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(UndefPair)
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.addReg(tmpRegLo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(tmpRegHi)
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.addImm(ARM::gsub_1);
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} else {
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// Copy to physregs for strexd
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(UndefPair)
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.addReg(vallo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair1)
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.addReg(r1)
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.addReg(valhi)
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.addImm(ARM::gsub_1);
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}
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// Store
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
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.addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
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.addReg(GPRPair1).addReg(ptr));
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// Cmp+jump
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(storesuccess).addImm(0));
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@ -417,6 +417,8 @@ def reglist : Operand<i32> {
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let DecoderMethod = "DecodeRegListOperand";
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}
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def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
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def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
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def dpr_reglist : Operand<i32> {
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let EncoderMethod = "getRegisterListOpValue";
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@ -4229,8 +4231,8 @@ def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary, "ldrex", "\t$Rt, $addr", []>;
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let hasExtraDefRegAllocReq = 1 in
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def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
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NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
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def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
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NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
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let DecoderMethod = "DecodeDoubleRegLoad";
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}
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}
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@ -4244,8 +4246,8 @@ def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
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let hasExtraSrcRegAllocReq = 1 in
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def STREXD : AIstrex<0b01, (outs GPR:$Rd),
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(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
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NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
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(ins GPRPairOp:$Rt, addr_offset_none:$addr),
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NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
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let DecoderMethod = "DecodeDoubleRegStore";
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}
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}
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@ -5187,6 +5187,45 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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}
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}
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// Adjust operands of ldrexd/strexd to MCK_GPRPair.
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// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
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// a single GPRPair reg operand is used in the .td file to replace the two
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// GPRs. However, when parsing from asm, the two GRPs cannot be automatically
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// expressed as a GPRPair, so we have to manually merge them.
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// FIXME: We would really like to be able to tablegen'erate this.
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if (!isThumb() && Operands.size() > 4 &&
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(Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
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bool isLoad = (Mnemonic == "ldrexd");
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unsigned Idx = isLoad ? 2 : 3;
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ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
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ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
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const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
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// Adjust only if Op1 and Op2 are GPRs.
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if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
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MRC.contains(Op2->getReg())) {
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unsigned Reg1 = Op1->getReg();
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unsigned Reg2 = Op2->getReg();
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unsigned Rt = MRI->getEncodingValue(Reg1);
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unsigned Rt2 = MRI->getEncodingValue(Reg2);
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// Rt2 must be Rt + 1 and Rt must be even.
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if (Rt + 1 != Rt2 || (Rt & 1)) {
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Error(Op2->getStartLoc(), isLoad ?
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"destination operands must be sequential" :
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"source operands must be sequential");
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return true;
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}
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unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
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&(MRI->getRegClass(ARM::GPRPairRegClassID)));
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Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
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Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
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NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
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delete Op1;
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delete Op2;
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}
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}
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return false;
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}
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@ -5274,8 +5313,7 @@ validateInstruction(MCInst &Inst,
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switch (Inst.getOpcode()) {
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case ARM::LDRD:
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case ARM::LDRD_PRE:
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case ARM::LDRD_POST:
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case ARM::LDREXD: {
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case ARM::LDRD_POST: {
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// Rt2 must be Rt + 1.
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unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
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unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
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@ -5294,8 +5332,7 @@ validateInstruction(MCInst &Inst,
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return false;
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}
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case ARM::STRD_PRE:
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case ARM::STRD_POST:
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case ARM::STREXD: {
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case ARM::STRD_POST: {
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// Rt2 must be Rt + 1.
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unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
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unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
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@ -7483,6 +7520,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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bool MatchingInlineAsm) {
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MCInst Inst;
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unsigned MatchResult;
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MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
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MatchingInlineAsm);
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switch (MatchResult) {
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@ -252,6 +252,35 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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return;
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}
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// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
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// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
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// a single GPRPair reg operand is used in the .td file to replace the two
|
||||
// GPRs. However, when decoding them, the two GRPs cannot be automatically
|
||||
// expressed as a GPRPair, so we have to manually merge them.
|
||||
// FIXME: We would really like to be able to tablegen'erate this.
|
||||
if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
|
||||
const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
|
||||
bool isStore = Opcode == ARM::STREXD;
|
||||
unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
|
||||
if (MRC.contains(Reg)) {
|
||||
MCInst NewMI;
|
||||
MCOperand NewReg;
|
||||
NewMI.setOpcode(Opcode);
|
||||
|
||||
if (isStore)
|
||||
NewMI.addOperand(MI->getOperand(0));
|
||||
NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
|
||||
&MRI.getRegClass(ARM::GPRPairRegClassID)));
|
||||
NewMI.addOperand(NewReg);
|
||||
|
||||
// Copy the rest operands into NewMI.
|
||||
for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
|
||||
NewMI.addOperand(MI->getOperand(i));
|
||||
printInstruction(&NewMI, O);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
printInstruction(MI, O);
|
||||
printAnnotation(O, Annot);
|
||||
}
|
||||
@ -691,6 +720,15 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
|
||||
O << "}";
|
||||
}
|
||||
|
||||
void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
unsigned Reg = MI->getOperand(OpNum).getReg();
|
||||
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
|
||||
O << ", ";
|
||||
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
|
||||
}
|
||||
|
||||
|
||||
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &Op = MI->getOperand(OpNum);
|
||||
|
||||
@ -124,6 +124,7 @@ public:
|
||||
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
|
||||
|
||||
define i64 @test1(i64* %ptr, i64 %val) {
|
||||
; CHECK: test1
|
||||
; CHECK: test1:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: adds r0, r2
|
||||
; CHECK: adc r1, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||
; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -15,12 +15,12 @@ define i64 @test1(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test2(i64* %ptr, i64 %val) {
|
||||
; CHECK: test2
|
||||
; CHECK: test2:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: subs r0, r2
|
||||
; CHECK: sbc r1, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||
; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -29,12 +29,12 @@ define i64 @test2(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test3(i64* %ptr, i64 %val) {
|
||||
; CHECK: test3
|
||||
; CHECK: test3:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: and r0, r2
|
||||
; CHECK: and r1, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||
; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -43,12 +43,12 @@ define i64 @test3(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test4(i64* %ptr, i64 %val) {
|
||||
; CHECK: test4
|
||||
; CHECK: test4:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: orr r0, r2
|
||||
; CHECK: orr r1, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||
; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -57,12 +57,12 @@ define i64 @test4(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test5(i64* %ptr, i64 %val) {
|
||||
; CHECK: test5
|
||||
; CHECK: test5:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: eor r0, r2
|
||||
; CHECK: eor r1, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||
; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -71,10 +71,10 @@ define i64 @test5(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test6(i64* %ptr, i64 %val) {
|
||||
; CHECK: test6
|
||||
; CHECK: test6:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -83,13 +83,13 @@ define i64 @test6(i64* %ptr, i64 %val) {
|
||||
}
|
||||
|
||||
define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
|
||||
; CHECK: test7
|
||||
; CHECK: test7:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: cmp r2
|
||||
; CHECK: cmpeq r3
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: cmp [[REG1]]
|
||||
; CHECK: cmpeq [[REG2]]
|
||||
; CHECK: bne
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -100,12 +100,12 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
|
||||
; Compiles down to cmpxchg
|
||||
; FIXME: Should compile to a single ldrexd
|
||||
define i64 @test8(i64* %ptr) {
|
||||
; CHECK: test8
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: cmp r2
|
||||
; CHECK: cmpeq r3
|
||||
; CHECK: test8:
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: cmp [[REG1]]
|
||||
; CHECK: cmpeq [[REG2]]
|
||||
; CHECK: bne
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
@ -116,10 +116,10 @@ define i64 @test8(i64* %ptr) {
|
||||
; Compiles down to atomicrmw xchg; there really isn't any more efficient
|
||||
; way to write it.
|
||||
define void @test9(i64* %ptr, i64 %val) {
|
||||
; CHECK: test9
|
||||
; CHECK: test9:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: strexd {{[a-z0-9]+}}, r0, r1
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
|
||||
@ -581,6 +581,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
|
||||
REG("cc_out");
|
||||
REG("s_cc_out");
|
||||
REG("tGPR");
|
||||
REG("GPRPairOp");
|
||||
REG("DPR");
|
||||
REG("DPR_VFP2");
|
||||
REG("DPR_8");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user