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[Hexagon] Use A2_tfrsi for constant pool and jump table addresses
llvm-svn: 235535
This commit is contained in:
Krzysztof Parzyszek
parent
ec41387ad6
commit
8605e42505
@ -116,12 +116,14 @@ static bool isCombinableInstType(MachineInstr *MI,
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switch(MI->getOpcode()) {
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case Hexagon::A2_tfr: {
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// A COPY instruction can be combined if its arguments are IntRegs (32bit).
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
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const MachineOperand &Op0 = MI->getOperand(0);
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const MachineOperand &Op1 = MI->getOperand(1);
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assert(Op0.isReg() && Op1.isReg());
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DestReg = Op0.getReg();
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unsigned SrcReg = Op1.getReg();
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return Hexagon::IntRegsRegClass.contains(DestReg) &&
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Hexagon::IntRegsRegClass.contains(SrcReg);
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Hexagon::IntRegsRegClass.contains(SrcReg);
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}
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case Hexagon::A2_tfrsi: {
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@ -144,21 +146,6 @@ static bool isCombinableInstType(MachineInstr *MI,
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(ShouldCombineAggressively || NotExt);
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}
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case Hexagon::TFRI_V4: {
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if (!ShouldCombineAggressively)
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return false;
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
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// Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
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// workaround for an ABI bug that prevents GOT relocations on combine
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// instructions
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if (MI->getOperand(1).getTargetFlags() != HexagonII::MO_NO_FLAG)
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return false;
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unsigned DestReg = MI->getOperand(0).getReg();
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return Hexagon::IntRegsRegClass.contains(DestReg);
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}
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default:
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break;
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}
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@ -166,13 +153,14 @@ static bool isCombinableInstType(MachineInstr *MI,
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return false;
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}
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static bool isGreaterThan8BitTFRI(MachineInstr *I) {
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return I->getOpcode() == Hexagon::A2_tfrsi &&
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!isInt<8>(I->getOperand(1).getImm());
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}
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static bool isGreaterThan6BitTFRI(MachineInstr *I) {
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return I->getOpcode() == Hexagon::A2_tfrsi &&
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!isUInt<6>(I->getOperand(1).getImm());
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template <unsigned N>
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static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
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if (I->getOpcode() == Hexagon::TFRI64_V4 ||
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I->getOpcode() == Hexagon::A2_tfrsi) {
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const MachineOperand &Op = I->getOperand(1);
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return !Op.isImm() || !isInt<N>(Op.getImm());
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}
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return false;
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}
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/// areCombinableOperations - Returns true if the two instruction can be merge
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@ -180,19 +168,15 @@ static bool isGreaterThan6BitTFRI(MachineInstr *I) {
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static bool areCombinableOperations(const TargetRegisterInfo *TRI,
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MachineInstr *HighRegInst,
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MachineInstr *LowRegInst) {
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assert((HighRegInst->getOpcode() == Hexagon::A2_tfr ||
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HighRegInst->getOpcode() == Hexagon::A2_tfrsi ||
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HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
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(LowRegInst->getOpcode() == Hexagon::A2_tfr ||
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LowRegInst->getOpcode() == Hexagon::A2_tfrsi ||
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LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
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unsigned HiOpc = HighRegInst->getOpcode();
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unsigned LoOpc = LowRegInst->getOpcode();
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assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
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(LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
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"Assume individual instructions are of a combinable type");
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// There is no combine of two constant extended values.
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if ((HighRegInst->getOpcode() == Hexagon::TFRI_V4 ||
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isGreaterThan8BitTFRI(HighRegInst)) &&
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(LowRegInst->getOpcode() == Hexagon::TFRI_V4 ||
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isGreaterThan6BitTFRI(LowRegInst)))
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if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
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isGreaterThanNBitTFRI<6>(LowRegInst))
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return false;
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return true;
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@ -219,10 +203,14 @@ static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
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unsigned DestReg,
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const TargetRegisterInfo *TRI) {
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return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
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I->modifiesRegister(DestReg, TRI) ||
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I->readsRegister(DestReg, TRI) ||
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I->hasUnmodeledSideEffects() ||
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I->isInlineAsm() || I->isDebugValue();
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I->modifiesRegister(DestReg, TRI) ||
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I->readsRegister(DestReg, TRI) ||
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I->hasUnmodeledSideEffects() ||
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I->isInlineAsm() || I->isDebugValue();
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}
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static unsigned UseReg(const MachineOperand& MO) {
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return MO.isReg() ? MO.getReg() : 0;
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}
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/// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
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@ -232,9 +220,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
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unsigned I1DestReg,
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unsigned I2DestReg,
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bool &DoInsertAtI1) {
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bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal();
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unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg();
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unsigned I2UseReg = UseReg(I2->getOperand(1));
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// It is not safe to move I1 and I2 into one combine if I2 has a true
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// dependence on I1.
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@ -298,8 +284,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
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// At O3 we got better results (dhrystone) by being more conservative here.
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if (!ShouldCombineAggressively)
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End = std::next(MachineBasicBlock::iterator(I2));
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IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
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unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
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unsigned I1UseReg = UseReg(I1->getOperand(1));
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// Track killed operands. If we move across an instruction that kills our
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// operand, we need to update the kill information on the moved I1. It kills
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// the operand now.
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@ -558,7 +543,7 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
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DebugLoc DL = InsertPt->getDebugLoc();
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MachineBasicBlock *BB = InsertPt->getParent();
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// Handle globals.
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// Handle globals.
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if (HiOperand.isGlobal()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
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.addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
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@ -574,17 +559,64 @@ void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
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return;
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}
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// Handle constant extended immediates.
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if (!isInt<8>(HiOperand.getImm())) {
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assert(isInt<8>(LoOperand.getImm()));
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// Handle block addresses.
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if (HiOperand.isBlockAddress()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
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HiOperand.getTargetFlags())
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.addImm(LoOperand.getImm());
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return;
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}
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if (LoOperand.isBlockAddress()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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return;
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}
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if (!isUInt<6>(LoOperand.getImm())) {
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assert(isInt<8>(HiOperand.getImm()));
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// Handle jump tables.
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if (HiOperand.isJTI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
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.addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
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.addImm(LoOperand.getImm());
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return;
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}
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if (LoOperand.isJTI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
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return;
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}
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// Handle constant pools.
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if (HiOperand.isCPI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
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.addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
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HiOperand.getTargetFlags())
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.addImm(LoOperand.getImm());
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return;
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}
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if (LoOperand.isCPI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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return;
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}
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// First preference should be given to Hexagon::A2_combineii instruction
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// as it can include U6 (in Hexagon::A4_combineii) as well.
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// In this instruction, HiOperand is const extended, if required.
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if (isInt<8>(LoOperand.getImm())) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addImm(LoOperand.getImm());
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return;
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}
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// In this instruction, LoOperand is const extended, if required.
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if (isInt<8>(HiOperand.getImm())) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
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.addImm(HiOperand.getImm())
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.addImm(LoOperand.getImm());
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@ -608,7 +640,7 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
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DebugLoc DL = InsertPt->getDebugLoc();
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MachineBasicBlock *BB = InsertPt->getParent();
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// Handle global.
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// Handle globals.
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if (HiOperand.isGlobal()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
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@ -616,6 +648,29 @@ void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
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.addReg(LoReg, LoRegKillFlag);
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return;
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}
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// Handle block addresses.
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if (HiOperand.isBlockAddress()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
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HiOperand.getTargetFlags())
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.addReg(LoReg, LoRegKillFlag);
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return;
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}
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// Handle jump tables.
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if (HiOperand.isJTI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
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.addReg(LoReg, LoRegKillFlag);
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return;
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}
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// Handle constant pools.
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if (HiOperand.isCPI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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.addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
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HiOperand.getTargetFlags())
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.addReg(LoReg, LoRegKillFlag);
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return;
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}
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// Insert new combine instruction.
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// DoubleRegDest = combine #HiImm, LoReg
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
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@ -641,6 +696,29 @@ void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
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LoOperand.getTargetFlags());
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return;
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}
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// Handle block addresses.
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if (LoOperand.isBlockAddress()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
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.addReg(HiReg, HiRegKillFlag)
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.addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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return;
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}
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// Handle jump tables.
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if (LoOperand.isJTI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
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.addReg(HiOperand.getReg(), HiRegKillFlag)
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.addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
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return;
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}
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// Handle constant pools.
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if (LoOperand.isCPI()) {
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
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.addReg(HiOperand.getReg(), HiRegKillFlag)
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.addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
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LoOperand.getTargetFlags());
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return;
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}
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// Insert new combine instruction.
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// DoubleRegDest = combine HiReg, #LoImm
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@ -1770,7 +1770,8 @@ bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
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// We currently only handle isGlobal() because it is the only kind of
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// object we are going to end up with here for now.
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// In the future we probably should add isSymbol(), etc.
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if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress())
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if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
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MO.isJTI() || MO.isCPI())
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return true;
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// If the extendable operand is not 'Immediate' type, the instruction should
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@ -4823,12 +4823,6 @@ def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
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[(set (i32 IntRegs:$dst),
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(load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
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let isReMaterializable = 1, isMoveImm = 1 in
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def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
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"$dst = CONST32(#$jt)",
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[(set (i32 IntRegs:$dst),
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(HexagonCONST32 tjumptable:$jt))]>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
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"$dst = CONST32(#$global)",
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@ -4836,7 +4830,7 @@ def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
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// Map TLS addressses to a CONST32 instruction
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def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
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def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
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def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
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@ -5145,10 +5139,8 @@ def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
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def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
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def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
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def: Pat<(HexagonJT tjumptable:$dst),
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(CONST32_set_jt tjumptable:$dst)>;
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def: Pat<(HexagonCP tconstpool :$dst),
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(CONST32_set_jt tconstpool:$dst)>;
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def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi s16Ext:$dst)>;
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def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi s16Ext:$dst)>;
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// XTYPE/SHIFT
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//
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@ -499,10 +499,23 @@ multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
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def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
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(HexagonCONST32 tglobaladdr:$src3)))),
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(MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
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def : Pat <(VT (ldOp (add IntRegs:$src1,
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(HexagonCONST32 tglobaladdr:$src2)))),
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(MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
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def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
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(HexagonCONST32 tconstpool:$src3)))),
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(MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
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def : Pat <(VT (ldOp (add IntRegs:$src1,
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(HexagonCONST32 tconstpool:$src2)))),
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(MI IntRegs:$src1, 0, tconstpool:$src2)>;
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def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
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(HexagonCONST32 tjumptable:$src3)))),
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(MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
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def : Pat <(VT (ldOp (add IntRegs:$src1,
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(HexagonCONST32 tjumptable:$src2)))),
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(MI IntRegs:$src1, 0, tjumptable:$src2)>;
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}
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let AddedComplexity = 60 in {
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@ -83,19 +83,8 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
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while (MII != MIE) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::CONST32_set_jt) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::A2_tfrsi), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_Int_Real &&
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MI->getOperand(1).isBlockAddress()) {
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if (Opc == Hexagon::CONST32_Int_Real &&
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MI->getOperand(1).isBlockAddress()) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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|
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@ -1,7 +1,8 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}})
|
||||
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}} + r{{[0-9]+<<#[0-9]+}})
|
||||
; Allow combine(..##JTI..):
|
||||
; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI
|
||||
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
|
||||
; CHECK: jumpr r{{[0-9]+}}
|
||||
|
||||
define void @main() #0 {
|
||||
|
||||
@ -27,7 +27,7 @@ entry:
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i64 @test4() #0 {
|
||||
; CHECK: combine(#0, ##100)
|
||||
; CHECK: combine(#0, #100)
|
||||
entry:
|
||||
store i16 100, i16* @b, align 2
|
||||
store i16 0, i16* @a, align 2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user