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Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.

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llvm-svn: 77557
This commit is contained in:
Bob Wilson 2009-07-30 00:31:25 +00:00
parent 79565c910c
commit 8624e45518
1 changed files with 19 additions and 1 deletions
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20
lib/Target/ARM/ARMISelLowering.cpp
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@ -2260,6 +2260,7 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
APInt SplatBits, SplatUndef;
unsigned SplatBitSize;
@ -2268,7 +2269,24 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
SplatUndef.getZExtValue(), SplatBitSize, DAG);
if (Val.getNode())
return BuildSplat(Val, Op.getValueType(), DAG, dl);
return BuildSplat(Val, VT, DAG, dl);
}
// If there are only 2 elements in a 128-bit vector, insert them into an
// undef vector. This handles the common case for 128-bit vector argument
// passing, where the insertions should be translated to subreg accesses
// with no real instructions.
if (VT.is128BitVector() && Op.getNumOperands() == 2) {
SDValue Val = DAG.getUNDEF(VT);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
if (Op0.getOpcode() != ISD::UNDEF)
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
DAG.getIntPtrConstant(0));
if (Op1.getOpcode() != ISD::UNDEF)
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
DAG.getIntPtrConstant(1));
return Val;
}
return SDValue();