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AMDGPU: Split 64-bit and of constant up
This breaks the tests that were meant for testing 64-bit inline immediates, so move those to shl where they won't be broken up. This should be repeated for the other related bit ops. llvm-svn: 258095
This commit is contained in:
Matt Arsenault
parent
6dde57e745
commit
862bf93c73
@ -28,7 +28,7 @@
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/DataLayout.h"
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#include "SIInstrInfo.h"
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using namespace llvm;
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static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
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@ -376,6 +376,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::MUL);
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@ -1177,6 +1178,21 @@ SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
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return SDValue();
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}
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std::pair<SDValue, SDValue>
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AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
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SDLoc SL(Op);
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SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
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const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
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const SDValue One = DAG.getConstant(1, SL, MVT::i32);
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SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
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SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
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return std::make_pair(Lo, Hi);
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}
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SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
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SelectionDAG &DAG) const {
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LoadSDNode *Load = cast<LoadSDNode>(Op);
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@ -2539,6 +2555,43 @@ SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
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SN->getBasePtr(), SN->getMemOperand());
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}
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// TODO: Should repeat for other bit ops.
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SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (N->getValueType(0) != MVT::i64)
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return SDValue();
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// Break up 64-bit and of a constant into two 32-bit ands. This will typically
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// happen anyway for a VALU 64-bit and. This exposes other 32-bit integer
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// combine opportunities since most 64-bit operations are decomposed this way.
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// TODO: We won't want this for SALU especially if it is an inline immediate.
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const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (!RHS)
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return SDValue();
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uint64_t Val = RHS->getZExtValue();
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if (Lo_32(Val) != 0 && Hi_32(Val) != 0 && !RHS->hasOneUse()) {
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// If either half of the constant is 0, this is really a 32-bit and, so
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// split it. If we can re-use the full materialized constant, keep it.
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return SDValue();
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}
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SDLoc SL(N);
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SelectionDAG &DAG = DCI.DAG;
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SDValue Lo, Hi;
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std::tie(Lo, Hi) = split64BitValue(N->getOperand(0), DAG);
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SDValue LoRHS = DAG.getConstant(Lo_32(Val), SL, MVT::i32);
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SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
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SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);
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SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);
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SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, LoAnd, HiAnd);
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return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
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}
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SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (N->getValueType(0) != MVT::i64)
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@ -2751,6 +2804,12 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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return performSrlCombine(N, DCI);
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}
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case ISD::AND: {
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if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
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break;
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return performAndCombine(N, DCI);
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}
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case ISD::MUL:
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return performMulCombine(N, DCI);
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case AMDGPUISD::MUL_I24:
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@ -67,21 +67,27 @@ private:
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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protected:
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS,
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DAGCombinerInfo &DCI) const;
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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protected:
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
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virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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/// Return 64-bit value Op as two 32-bit integers.
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std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
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SelectionDAG &DAG) const;
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/// \brief Split a vector load into a scalar load of each component.
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SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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@ -1915,6 +1915,9 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI))
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return Base;
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SelectionDAG &DAG = DCI.DAG;
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// (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
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@ -177,14 +177,62 @@ define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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; FUNC-LABEL: {{^}}s_and_constant_i64:
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}}
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}}
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; SI: buffer_store_dwordx2
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define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
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%and = and i64 %a, 281474976710655
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%and = and i64 %a, 549756338176
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64:
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; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}}
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; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}}
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; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
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define void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%and0 = and i64 %a, 549756338176
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%and1 = and i64 %b, 549756338176
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store volatile i64 %and0, i64 addrspace(1)* %out
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store volatile i64 %and1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64:
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}}
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i64 %a) {
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64:
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 62
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 62
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i64 %c) {
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%shl.a = shl i64 %a, 1
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%shl.b = shl i64 %b, 1
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%and0 = and i64 %shl.a, 62
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%and1 = and i64 %shl.b, 62
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%add0 = add i64 %and0, %c
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%add1 = add i64 %and1, %c
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store volatile i64 %add0, i64 addrspace(1)* %out
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store volatile i64 %add1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64:
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; SI: v_and_b32
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; SI: v_and_b32
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@ -217,10 +265,8 @@ endif:
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}
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; FUNC-LABEL: {{^}}v_and_constant_i64:
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; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207
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; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}}
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; SI: buffer_store_dwordx2
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define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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@ -229,10 +275,54 @@ define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr)
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ret void
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}
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; FIXME: Should replace and 0
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; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64:
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; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
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; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
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; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}}
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; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]]
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; SI: buffer_store_dwordx2
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; SI: buffer_store_dwordx2
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define void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load volatile i64, i64 addrspace(1)* %aptr
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%b = load volatile i64, i64 addrspace(1)* %aptr
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%and0 = and i64 %a, 1231231234567
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%and1 = and i64 %b, 1231231234567
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store volatile i64 %and0, i64 addrspace(1)* %out
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store volatile i64 %and1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64:
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; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
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; SI-NOT: and
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; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
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; SI-NOT: and
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; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]]
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; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]]
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load volatile i64, i64 addrspace(1)* %aptr
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%b = load volatile i64, i64 addrspace(1)* %aptr
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%and0 = and i64 %a, 63
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%and1 = and i64 %b, 63
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store volatile i64 %and0, i64 addrspace(1)* %out
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store volatile i64 %and1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant:
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; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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; SI: buffer_load_dword [[VAL:v[0-9]+]]
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; SI-NOT: and
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]]
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1234567
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@ -240,10 +330,12 @@ define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)*
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ret void
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}
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; FIXME: Replace and 0 with mov 0
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; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
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; SI: buffer_load_dword v{{[0-9]+}}
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; SI-NOT: and
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; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 64
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@ -252,15 +344,38 @@ define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %apt
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64
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; SI: s_load_dword
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64
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; SI-NOT: and
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; SI: buffer_store_dword
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define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 64
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink:
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; SI: s_lshl_b64 s{{\[}}[[VALLO:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s[[VALLO]], 64
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; SI-NOT: and
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; SI: s_add_u32
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; SI-NEXT: s_addc_u32
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define void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i64 %b) {
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%shl = shl i64 %a, 1
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%and = and i64 %shl, 64
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%add = add i64 %and, %b
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store i64 %add, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 1
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store i64 %and, i64 addrspace(1)* %out, align 8
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@ -268,7 +383,14 @@ define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 4607182418800017408
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
@ -276,7 +398,14 @@ define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)*
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 13830554455654793216
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
@ -284,47 +413,85 @@ define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 4602678819172646912
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64:
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 13826050856027422720
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64:
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 4611686018427387904
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64:
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 13835058055282163712
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64:
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 4616189618054758400
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64:
|
||||
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
|
||||
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 13839561654909534208
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
@ -335,22 +502,26 @@ define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(
|
||||
; Test with the 64-bit integer bitpattern for a 32-bit float in the
|
||||
; low 32-bits, which is not a valid 64-bit inline immmediate.
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64:
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dword s
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 1082130432
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Copy of -1 register
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
|
||||
; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}
|
||||
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64:
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, -1065353216
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
@ -358,20 +529,25 @@ define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrsp
|
||||
}
|
||||
|
||||
; Shift into upper 32-bits
|
||||
; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 4647714815446351872
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
|
||||
; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
|
||||
; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64:
|
||||
; SI: s_load_dwordx2
|
||||
; SI: s_load_dwordx2
|
||||
; SI-NOT: and
|
||||
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
|
||||
; SI-NOT: and
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%and = and i64 %a, 13871086852301127680
|
||||
store i64 %and, i64 addrspace(1)* %out, align 8
|
||||
|
||||
@ -50,15 +50,18 @@ define void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure the and of the constant doesn't prevent bfe from forming
|
||||
; after 64-bit shift is split.
|
||||
|
||||
; GCN-LABEL: {{^}}lshr_and_i64_35:
|
||||
; XGCN: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; XGCN: v_lshlrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]]
|
||||
; XGCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
|
||||
; XGCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
||||
; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
|
||||
; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23
|
||||
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
|
||||
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}}
|
||||
define void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
%val = load i64, i64 addrspace(1)* %in
|
||||
%and = and i64 %val, 2147483647 ; 0x7fffffff
|
||||
%shl = lshr i64 %and, 35
|
||||
%and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff
|
||||
%shl = lshr i64 %and, 40
|
||||
store i64 %shl, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -208,4 +208,173 @@ define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_constant_i64
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
define void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) {
|
||||
%shl = shl i64 281474976710655, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_shl_constant_i64:
|
||||
; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207
|
||||
; SI-DAG: s_movk_i32 s[[KHI:[0-9]+]], 0x11e{{$}}
|
||||
; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
|
||||
; SI: buffer_store_dwordx2
|
||||
define void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
||||
%a = load i64, i64 addrspace(1)* %aptr, align 8
|
||||
%shl = shl i64 1231231234567, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_shl_i64_32_bit_constant:
|
||||
; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}}
|
||||
; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}}
|
||||
; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
|
||||
define void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
||||
%a = load i64, i64 addrspace(1)* %aptr, align 8
|
||||
%shl = shl i64 1234567, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_shl_inline_imm_64_i64:
|
||||
; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}}
|
||||
define void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
||||
%a = load i64, i64 addrspace(1)* %aptr, align 8
|
||||
%shl = shl i64 64, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_64_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 64, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_1_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 1, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_1.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 4607182418800017408, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_1.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 13830554455654793216, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_0.5_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 4602678819172646912, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_0.5_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 13826050856027422720, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_2.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 4611686018427387904, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_2.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 13835058055282163712, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_4.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 4616189618054758400, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_4.0_i64:
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -4.0, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 13839561654909534208, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; Test with the 64-bit integer bitpattern for a 32-bit float in the
|
||||
; low 32-bits, which is not a valid 64-bit inline immmediate.
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_4.0_i64:
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 1082130432, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Copy of -1 register
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_neg_4.0_i64:
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
|
||||
; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}, s{{[0-9]+}}
|
||||
define void @s_shl_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 -1065353216, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Shift into upper 32-bits
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_4.0_i64:
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
|
||||
define void @s_shl_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 4647714815446351872, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_neg_4.0_i64:
|
||||
; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
|
||||
; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
|
||||
; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
|
||||
define void @s_shl_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
||||
%shl = shl i64 13871086852301127680, %a
|
||||
store i64 %shl, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user