RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-04 17:56:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

reapply r103668 with a fix. Never make "minor syntax changes"

Browse Source 
after testing before committing.

llvm-svn: 103681
This commit is contained in:
Chris Lattner 2010-05-13 00:02:47 +00:00
parent 791573787a
commit 887e8f9f53
4 changed files with 43 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -622,6 +622,31 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
return false;
}
/// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
/// imm operand, to having "rm" or "mr" operands with the offset in the disp
/// field.
static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
bool isMR) {
MCOperand Disp = Inst.getOperand(0);
// Start over with an empty instruction.
Inst = MCInst();
Inst.setOpcode(Opc);
if (!isMR)
Inst.addOperand(MCOperand::CreateReg(RegNo));
// Add the mem operand.
Inst.addOperand(MCOperand::CreateReg(0)); // Segment
Inst.addOperand(MCOperand::CreateImm(1)); // Scale
Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
Inst.addOperand(Disp); // Displacement
Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
if (isMR)
Inst.addOperand(MCOperand::CreateReg(RegNo));
}
// FIXME: Custom X86 cleanup function to implement a temporary hack to handle
// matching INCL/DECL correctly for x86_64. This needs to be replaced by a
// proper mechanism for supporting (ambiguous) feature dependent instructions.
@ -637,6 +662,14 @@ void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
// moffset instructions are x86-32 only.
case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
}
}

4
lib/Target/X86/X86InstrInfo.td
View File

@ -966,8 +966,8 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[(store (i32 imm:$src), addr:$dst)]>;
/// moffs8, moffs16, moffs32 and moffs64 versions of moves. The immediate is a
/// 32-bit offset from the PC.
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
/// 32-bit offset from the PC. These are only valid in x86-32 mode.
def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
"mov{b}\t{$src, %al|%al, $src}", []>;
def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),

1
test/MC/AsmParser/X86/x86_32-new-encoder.s
View File

@ -52,7 +52,6 @@ rdtscp
shrl $1, %eax
// moffset forms of moves, rdar://7947184
movb 0, %al // CHECK: movb 0, %al # encoding: [0xa0,A,A,A,A]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0xa1,A,A,A,A]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0xa1,A,A,A,A]

7
test/MC/AsmParser/X86/x86_64-new-encoder.s
View File

@ -69,3 +69,10 @@ stosq
stosl
// CHECK: stosl
// CHECK: encoding: [0xab]
// Not moffset forms of moves, they are x86-32 only! rdar://7947184
movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,A,A,A,A]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,A,A,A,A]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,A,A,A,A]