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AMDGPU: llvm.amdgcn.writelane is a source of divergence
Summary: Consider: %r = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) This produces a value that is 0 on lane 1, and 2 everywhere else; i.e., it is divergent. Reported-by: Marek Olsak <Marek.Olsak@amd.com> Reviewers: arsenm, foad, mareko Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74400
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@ -247,6 +247,7 @@ def : SourceOfDivergence<int_amdgcn_permlanex16>;
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def : SourceOfDivergence<int_amdgcn_mov_dpp>;
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def : SourceOfDivergence<int_amdgcn_mov_dpp8>;
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def : SourceOfDivergence<int_amdgcn_update_dpp>;
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def : SourceOfDivergence<int_amdgcn_writelane>;
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def : SourceOfDivergence<int_amdgcn_mfma_f32_4x4x1f32>;
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def : SourceOfDivergence<int_amdgcn_mfma_f32_4x4x1f32>;
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@ -42,12 +42,20 @@ define amdgpu_kernel void @mov_dpp8(i32 addrspace(1)* %out, i32 %in) #0 {
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ret void
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}
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; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2)
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define amdgpu_kernel void @writelane(i32 addrspace(1)* %out) #0 {
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%tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2)
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store i32 %tmp0, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1
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declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) #1
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declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) #1
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declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #1
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declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #1
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declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #1
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attributes #0 = { nounwind convergent }
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attributes #1 = { nounwind readnone convergent }
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