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Rename ConstantSDNode::getValue to getZExtValue, for consistency

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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
This commit is contained in:
Dan Gohman 2008-09-12 16:56:44 +00:00
parent 05a3e3ea40
commit 89660301e3
44 changed files with 542 additions and 482 deletions
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2
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -1715,7 +1715,7 @@ protected:
public:
const APInt &getAPIntValue() const { return Value; }
uint64_t getValue() const { return Value.getZExtValue(); }
uint64_t getZExtValue() const { return Value.getZExtValue(); }
int64_t getSignExtended() const {
unsigned Bits = getValueType(0).getSizeInBits();

89
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1988,8 +1988,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
if (LHSShiftAmt.getOpcode() == ISD::Constant &&
RHSShiftAmt.getOpcode() == ISD::Constant) {
uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
@ -2300,7 +2300,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (N0C && N0C->isNullValue())
return N0;
// fold (shl x, c >= size(x)) -> undef
if (N1C && N1C->getValue() >= OpSizeInBits)
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
return DAG.getNode(ISD::UNDEF, VT);
// fold (shl x, 0) -> x
if (N1C && N1C->isNullValue())
@ -2319,12 +2319,13 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
MVT TruncVT = N1.getValueType();
unsigned TruncBitSize = TruncVT.getSizeInBits();
APInt ShAmt = N101C->getAPIntValue();
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getValue()) {
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
SDValue N100 = N1.getOperand(0).getOperand(0);
return DAG.getNode(ISD::SHL, VT, N0,
DAG.getNode(ISD::AND, TruncVT,
DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
DAG.getConstant(N101C->getValue(), TruncVT)));
DAG.getConstant(N101C->getZExtValue(),
TruncVT)));
}
}
}
@ -2334,8 +2335,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
uint64_t c2 = N1C->getValue();
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
if (c1 + c2 > OpSizeInBits)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
@ -2345,8 +2346,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// (srl (and x, -1 << c1), c1-c2)
if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
uint64_t c2 = N1C->getValue();
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << c1, VT));
if (c2 > c1)
@ -2359,9 +2360,9 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << N1C->getValue(), VT));
DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
}
SDValue DAGCombiner::visitSRA(SDNode *N) {
@ -2381,7 +2382,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
if (N0C && N0C->isAllOnesValue())
return N0;
// fold (sra x, c >= size(x)) -> undef
if (N1C && N1C->getValue() >= VT.getSizeInBits())
if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
return DAG.getNode(ISD::UNDEF, VT);
// fold (sra x, 0) -> x
if (N1C && N1C->isNullValue())
@ -2389,7 +2390,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
// sext_inreg.
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
MVT EVT = MVT::getIntegerVT(LowBits);
if (EVT.isSimple() && // TODO: remove when apint codegen support lands.
(!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
@ -2400,7 +2401,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SRA) {
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
unsigned Sum = N1C->getValue() + C1->getValue();
unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
DAG.getConstant(Sum, N1C->getValueType(0)));
@ -2419,9 +2420,9 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
// Determine what the truncate's result bitsize and type would be.
unsigned VTValSize = VT.getSizeInBits();
MVT TruncVT =
MVT::getIntegerVT(VTValSize - N1C->getValue());
MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
// Determine the residual right-shift amount.
unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
// If the shift is not a no-op (in which case this should be just a sign
// extend already), the truncated to type is legal, sign_extend is legal
@ -2450,12 +2451,13 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
MVT TruncVT = N1.getValueType();
unsigned TruncBitSize = TruncVT.getSizeInBits();
APInt ShAmt = N101C->getAPIntValue();
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getValue()) {
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
SDValue N100 = N1.getOperand(0).getOperand(0);
return DAG.getNode(ISD::SRA, VT, N0,
DAG.getNode(ISD::AND, TruncVT,
DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
DAG.getConstant(N101C->getValue(), TruncVT)));
DAG.getConstant(N101C->getZExtValue(),
TruncVT)));
}
}
}
@ -2469,7 +2471,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SRL, VT, N0, N1);
return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
}
SDValue DAGCombiner::visitSRL(SDNode *N) {
@ -2487,7 +2489,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N0C && N0C->isNullValue())
return N0;
// fold (srl x, c >= size(x)) -> undef
if (N1C && N1C->getValue() >= OpSizeInBits)
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
return DAG.getNode(ISD::UNDEF, VT);
// fold (srl x, 0) -> x
if (N1C && N1C->isNullValue())
@ -2500,8 +2502,8 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
uint64_t c2 = N1C->getValue();
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t c2 = N1C->getZExtValue();
if (c1 + c2 > OpSizeInBits)
return DAG.getConstant(0, VT);
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
@ -2512,7 +2514,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
MVT SmallVT = N0.getOperand(0).getValueType();
if (N1C->getValue() >= SmallVT.getSizeInBits())
if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
return DAG.getNode(ISD::UNDEF, VT);
SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
@ -2522,7 +2524,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
// bit, which is unmodified by sra.
if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) {
if (N0.getOpcode() == ISD::SRA)
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
}
@ -2570,12 +2572,13 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
MVT TruncVT = N1.getValueType();
unsigned TruncBitSize = TruncVT.getSizeInBits();
APInt ShAmt = N101C->getAPIntValue();
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getValue()) {
if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
SDValue N100 = N1.getOperand(0).getOperand(0);
return DAG.getNode(ISD::SRL, VT, N0,
DAG.getNode(ISD::AND, TruncVT,
DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
DAG.getConstant(N101C->getValue(), TruncVT)));
DAG.getConstant(N101C->getZExtValue(),
TruncVT)));
}
}
}
@ -2585,7 +2588,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
}
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
@ -3188,7 +3191,7 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
break;
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
// See if we can recursively simplify the LHS.
unsigned Amt = RHSC->getValue();
unsigned Amt = RHSC->getZExtValue();
APInt NewMask = Mask << Amt;
SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
if (SimplifyLHS.getNode()) {
@ -3230,7 +3233,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
bool CombineSRL = false;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
ShAmt = N01->getValue();
ShAmt = N01->getZExtValue();
// Is the shift amount a multiple of size of VT?
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
@ -3340,11 +3343,11 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
if (N0.getOpcode() == ISD::SRL) {
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
// We can turn this into an SRA iff the input to the SRL is already sign
// extended enough.
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
}
}
@ -4775,7 +4778,7 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
// If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
// vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
InVec.getNode()->op_end());
if (Elt < Ops.size())
@ -4800,7 +4803,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
bool NewLoad = false;
MVT VT = InVec.getValueType();
MVT EVT = VT.getVectorElementType();
@ -4826,7 +4829,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// =>
// (load $addr+1*size)
unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
getOperand(Elt))->getValue();
getOperand(Elt))->getZExtValue();
unsigned NumElems = InVec.getOperand(2).getNumOperands();
InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
if (InVec.getOpcode() == ISD::BIT_CONVERT)
@ -4930,7 +4933,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
}
// Otherwise, use InIdx + VecSize
unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
unsigned Idx =
cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
}
@ -4981,7 +4985,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
bool isIdentity = true;
for (unsigned i = 0; i != NumElts; ++i) {
if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
isIdentity = false;
break;
}
@ -4992,7 +4996,8 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
isIdentity = true;
for (unsigned i = 0; i != NumElts; ++i) {
if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
i+NumElts) {
isIdentity = false;
break;
}
@ -5007,7 +5012,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
unsigned BaseIdx = 0;
for (unsigned i = 0; i != NumElts; ++i)
if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
int V = (Idx < NumElts) ? 0 : 1;
if (VecNum == -1) {
VecNum = V;
@ -5078,11 +5083,13 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
SmallVector<SDValue, 8> MappedOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
NumElts) {
MappedOps.push_back(ShufMask.getOperand(i));
} else {
unsigned NewIdx =
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
NumElts;
MappedOps.push_back(DAG.getConstant(NewIdx,
ShufMask.getOperand(i).getValueType()));
}
@ -5556,7 +5563,7 @@ static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
if (Base.getOpcode() == ISD::ADD) {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
Base = Base.getOperand(0);
Offset += C->getValue();
Offset += C->getZExtValue();
}
}

39
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -249,7 +249,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
if (InOp.getOpcode() == ISD::UNDEF)
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
else {
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
}
}
@ -1376,7 +1376,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp1 = LegalizeOp(Node->getOperand(0));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
assert(idx && "Operand must be a constant");
Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
}
break;
@ -1385,7 +1385,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp2 = LegalizeOp(Node->getOperand(1));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
assert(idx && "Operand must be a constant");
Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
}
break;
@ -1451,7 +1451,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// elt 0 of the RHS.
SmallVector<SDValue, 8> ShufOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (i != InsertPos->getValue())
if (i != InsertPos->getZExtValue())
ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
else
ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
@ -1527,7 +1527,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
} else {
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Idx < NumElems)
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
DAG.getConstant(Idx, PtrVT)));
@ -1687,7 +1687,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
SDValue Size = Tmp2.getOperand(1);
SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
unsigned StackAlign =
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
if (Align > StackAlign)
@ -1734,7 +1734,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
for (++i; NumVals; ++i, --NumVals) {
SDValue Op = LegalizeOp(Ops[i]);
if (Op != Ops[i]) {
@ -2168,7 +2168,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
switch (getTypeAction(OpTy)) {
default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
case Legal:
if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
// 1 -> Hi
Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
DAG.getConstant(OpTy.getSizeInBits()/2,
@ -2183,7 +2183,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
case Expand:
// Get both the low and high parts.
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
Result = Tmp2; // 1 -> Hi
else
Result = Tmp1; // 0 -> Lo
@ -4554,11 +4554,11 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
SDValue Lo, Hi;
SplitVectorOp(Vec, Lo, Hi);
if (CIdx->getValue() < NumLoElts) {
if (CIdx->getZExtValue() < NumLoElts) {
Vec = Lo;
} else {
Vec = Hi;
Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
Idx.getValueType());
}
@ -4606,11 +4606,12 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
SDValue Lo, Hi;
SplitVectorOp(Vec, Lo, Hi);
if (CIdx->getValue() < NumElems/2) {
if (CIdx->getZExtValue() < NumElems/2) {
Vec = Lo;
} else {
Vec = Hi;
Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
Idx.getValueType());
}
// It's now an extract from the appropriate high or low part. Recurse.
@ -5138,7 +5139,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
// Handle the case when Amt is an immediate.
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
unsigned Cst = CN->getValue();
unsigned Cst = CN->getZExtValue();
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
ExpandOp(Op, InL, InH);
@ -5876,7 +5877,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
abort();
case ISD::EXTRACT_ELEMENT:
ExpandOp(Node->getOperand(0), Lo, Hi);
if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
return ExpandOp(Hi, Lo, Hi);
return ExpandOp(Lo, Lo, Hi);
case ISD::EXTRACT_VECTOR_ELT:
@ -6863,7 +6864,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
case ISD::INSERT_VECTOR_ELT: {
if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
SplitVectorOp(Node->getOperand(0), Lo, Hi);
unsigned Index = Idx->getValue();
unsigned Index = Idx->getZExtValue();
SDValue ScalarOp = Node->getOperand(1);
if (Index < NewNumElts_Lo)
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
@ -6894,7 +6895,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
SDValue InVec = Node->getOperand(0);
if (Idx >= NumElements) {
InVec = Node->getOperand(1);
@ -6912,7 +6913,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
SDValue InVec = Node->getOperand(0);
if (Idx >= NumElements) {
InVec = Node->getOperand(1);
@ -7240,7 +7241,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
case ISD::VECTOR_SHUFFLE: {
// Figure out if the scalar is the LHS or RHS and return it.
SDValue EltNum = Node->getOperand(2).getOperand(0);
if (cast<ConstantSDNode>(EltNum)->getValue())
if (cast<ConstantSDNode>(EltNum)->getZExtValue())
Result = ScalarizeVectorOp(Node->getOperand(1));
else
Result = ScalarizeVectorOp(Node->getOperand(0));

2
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1481,7 +1481,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
// If we can emit an efficient shift operation, do so now. Check to see if
// the RHS is a constant.
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
// If we can determine that the high bit of the shift is zero or one, even if
// the low bits are variable, emit this shift in an optimized form.

5
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -88,7 +88,8 @@ void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
GetExpandedOp(N->getOperand(0), Lo, Hi);
SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ?
Hi : Lo;
assert(Part.getValueType() == N->getValueType(0) &&
"Type twice as big as expanded type not itself expanded!");
@ -233,7 +234,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
SDValue Lo, Hi;
GetExpandedOp(N->getOperand(0), Lo, Hi);
return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ? Hi : Lo;
}
SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {

14
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -157,7 +157,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
// Figure out if the scalar is the LHS or RHS and return it.
SDValue EltNum = N->getOperand(2).getOperand(0);
unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
unsigned Op = cast<ConstantSDNode>(EltNum)->getZExtValue() != 0;
return GetScalarizedVector(N->getOperand(Op));
}
@ -450,7 +450,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
GetSplitVector(Vec, Lo, Hi);
if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
unsigned IdxVal = CIdx->getValue();
unsigned IdxVal = CIdx->getZExtValue();
unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
if (IdxVal < LoNumElts)
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
@ -562,7 +562,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
// buildvector of extractelement here because the input vectors will have
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != LoNumElts; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
@ -575,7 +575,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
Ops.clear();
for (unsigned i = LoNumElts; i != NumElements; ++i) {
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
SDValue InVec = N->getOperand(0);
if (Idx >= NumElements) {
InVec = N->getOperand(1);
@ -677,7 +677,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
GetSplitVector(N->getOperand(0), Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
if (IdxVal < LoElts) {
assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
@ -695,7 +695,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
MVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
SDValue Lo, Hi;
@ -803,7 +803,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
SmallVector<SDValue, 16> Ops(MaskLength);
for (unsigned i = 0; i < MaskLength; ++i) {
uint64_t Idx =
cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
Ops[i] = DAG.getConstant(Idx, OpVT);
}
return DAG.UpdateNodeOperands(SDValue(N,0),

11
lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
View File

@ -254,7 +254,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
}
#endif
} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
MI->addOperand(MachineOperand::CreateImm(C->getValue()));
MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
ConstantFP *CFP = ConstantFP::get(F->getValueAPF());
MI->addOperand(MachineOperand::CreateFPImm(CFP));
@ -363,7 +363,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
}
if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
// Create the extract_subreg machine instruction.
MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
@ -397,7 +397,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
SDValue N1 = Node->getOperand(1);
SDValue N2 = Node->getOperand(2);
unsigned SubReg = getVR(N1, VRBaseMap);
unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
// Figure out the register class to create for the destreg.
@ -419,7 +419,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
// is an implicit value immediate, otherwise it's a register
if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
} else
AddOperand(MI, N0, 0, 0, VRBaseMap);
// Add the subregster being inserted
@ -577,7 +577,8 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned Flags =
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
unsigned NumVals = Flags >> 3;
MI->addOperand(MachineOperand::CreateImm(Flags));

59
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1462,7 +1462,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
case ISD::SHL:
// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -1480,7 +1480,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
case ISD::SRL:
// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -1498,7 +1498,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
return;
case ISD::SRA:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -1823,7 +1823,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
// SRA X, C -> adds C sign bits.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Tmp += C->getValue();
Tmp += C->getZExtValue();
if (Tmp > VTBits) Tmp = VTBits;
}
return Tmp;
@ -1831,9 +1831,9 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
// shl destroys sign bits.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
if (C->getValue() >= VTBits || // Bad shift.
C->getValue() >= Tmp) break; // Shifted all sign bits out.
return Tmp - C->getValue();
if (C->getZExtValue() >= VTBits || // Bad shift.
C->getZExtValue() >= Tmp) break; // Shifted all sign bits out.
return Tmp - C->getZExtValue();
}
break;
case ISD::AND:
@ -1865,7 +1865,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
case ISD::ROTL:
case ISD::ROTR:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned RotAmt = C->getValue() & (VTBits-1);
unsigned RotAmt = C->getZExtValue() & (VTBits-1);
// Handle rotate right by N like a rotate left by 32-N.
if (Op.getOpcode() == ISD::ROTR)
@ -2008,7 +2008,7 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
SDValue Idx = PermMask.getOperand(i);
if (Idx.getOpcode() == ISD::UNDEF)
return getNode(ISD::UNDEF, VT.getVectorElementType());
unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
unsigned NumElems = PermMask.getNumOperands();
SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
Index %= NumElems;
@ -2389,14 +2389,15 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
unsigned Factor =
N1.getOperand(0).getValueType().getVectorNumElements();
return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
N1.getOperand(N2C->getValue() / Factor),
getConstant(N2C->getValue() % Factor, N2.getValueType()));
N1.getOperand(N2C->getZExtValue() / Factor),
getConstant(N2C->getZExtValue() % Factor,
N2.getValueType()));
}
// EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
// expanding large vector constants.
if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR)
return N1.getOperand(N2C->getValue());
return N1.getOperand(N2C->getZExtValue());
// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
// operations are lowered to scalars.
@ -2408,7 +2409,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
}
break;
case ISD::EXTRACT_ELEMENT:
assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!");
assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!");
assert(!N1.getValueType().isVector() && !VT.isVector() &&
(N1.getValueType().isInteger() == VT.isInteger()) &&
"Wrong types for EXTRACT_ELEMENT!");
@ -2417,12 +2418,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
// 64-bit integers into 32-bit parts. Instead of building the extract of
// the BUILD_PAIR, only to have legalize rip it apart, just do it now.
if (N1.getOpcode() == ISD::BUILD_PAIR)
return N1.getOperand(N2C->getValue());
return N1.getOperand(N2C->getZExtValue());
// EXTRACT_ELEMENT of a constant int is also very common.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
unsigned ElementSize = VT.getSizeInBits();
unsigned Shift = ElementSize * N2C->getValue();
unsigned Shift = ElementSize * N2C->getZExtValue();
APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
return getConstant(ShiftedVal.trunc(ElementSize), VT);
}
@ -2638,7 +2639,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
}
case ISD::SELECT:
if (N1C) {
if (N1C->getValue())
if (N1C->getZExtValue())
return N2; // select true, X, Y -> X
else
return N3; // select false, X, Y -> Y
@ -2648,7 +2649,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
break;
case ISD::BRCOND:
if (N2C) {
if (N2C->getValue()) // Unconditional branch
if (N2C->getZExtValue()) // Unconditional branch
return getNode(ISD::BR, MVT::Other, N1, N3);
else
return N1; // Never-taken branch
@ -2712,7 +2713,7 @@ static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) {
unsigned NumBits = VT.isVector() ?
VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
APInt Val = APInt(NumBits, C->getValue() & 255);
APInt Val = APInt(NumBits, C->getZExtValue() & 255);
unsigned Shift = 8;
for (unsigned i = NumBits; i > 8; i >>= 1) {
Val = (Val << Shift) | Val;
@ -2783,7 +2784,7 @@ static bool isMemSrcFromString(SDValue Src, std::string &Str) {
Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
Src.getOperand(1).getOpcode() == ISD::Constant) {
G = cast<GlobalAddressSDNode>(Src.getOperand(0));
SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getValue();
SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
}
if (!G)
return false;
@ -3047,7 +3048,8 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
return Chain;
SDValue Result =
getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
ConstantSize->getZExtValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
return Result;
@ -3067,7 +3069,7 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
if (AlwaysInline) {
assert(ConstantSize && "AlwaysInline requires a constant size!");
return getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
ConstantSize->getValue(), Align, true,
ConstantSize->getZExtValue(), Align, true,
DstSV, DstSVOff, SrcSV, SrcSVOff);
}
@ -3101,7 +3103,8 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst,
return Chain;
SDValue Result =
getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(),
getMemmoveLoadsAndStores(*this, Chain, Dst, Src,
ConstantSize->getZExtValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
return Result;
@ -3144,8 +3147,8 @@ SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst,
return Chain;
SDValue Result =
getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getValue(), Align,
DstSV, DstSVOff);
getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(),
Align, DstSV, DstSVOff);
if (Result.getNode())
return Result;
}
@ -4768,7 +4771,7 @@ bool SDNode::isPredecessorOf(SDNode *N) const {
uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
assert(Num < NumOperands && "Invalid child # of SDNode!");
return cast<ConstantSDNode>(OperandList[Num])->getValue();
return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
}
std::string SDNode::getOperationName(const SelectionDAG *G) const {
@ -4875,12 +4878,12 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::ConstantPool: return "ConstantPool";
case ISD::ExternalSymbol: return "ExternalSymbol";
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IID = cast<ConstantSDNode>(getOperand(0))->getValue();
unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue();
return Intrinsic::getName((Intrinsic::ID)IID);
}
case ISD::INTRINSIC_VOID:
case ISD::INTRINSIC_W_CHAIN: {
unsigned IID = cast<ConstantSDNode>(getOperand(1))->getValue();
unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue();
return Intrinsic::getName((Intrinsic::ID)IID);
}
@ -5128,7 +5131,7 @@ void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
if (Mask->getOperand(i).getOpcode() == ISD::UNDEF)
OS << "u";
else
OS << cast<ConstantSDNode>(Mask->getOperand(i))->getValue();
OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue();
}
OS << ">";
}

6
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -3601,7 +3601,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
// lower memmove as memcpy.
uint64_t Size = -1ULL;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
Size = C->getValue();
Size = C->getZExtValue();
if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
AliasAnalysis::NoAlias) {
DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
@ -4957,7 +4957,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
for (; OperandNo; --OperandNo) {
// Advance to the next operand.
unsigned NumOps =
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
(NumOps & 7) == 4 /*MEM*/) &&
"Skipped past definitions?");
@ -4965,7 +4965,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
}
unsigned NumOps =
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
if ((NumOps & 7) == 2 /*REGDEF*/) {
// Add NumOps>>3 registers to MatchedRegs.
RegsForValue MatchedRegs;

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -406,7 +406,7 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
SDValue OpRet(Ret, 0);
SDValue OpCall(BI, 0);
bool isMarkedTailCall =
cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
cast<ConstantSDNode>(OpCall.getOperand(3))->getZExtValue() != 0;
// If CALL node has tail call attribute set to true and the call is not
// eligible (no RET or the target rejects) the attribute is fixed to
// false. The TargetLowering::IsEligibleForTailCallOptimization function
@ -1122,7 +1122,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
--e; // Don't process a flag operand if it is here.
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
if ((Flags & 7) != 4 /*MEM*/) {
// Just skip over this operand, copying the operands verbatim.
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);

2
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -121,7 +121,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
std::string Op = Node->getOperationName(G);
if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(Node)) {
Op += ": " + utostr(CSDN->getValue());
Op += ": " + utostr(CSDN->getZExtValue());
} else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) {
Op += ": " + ftostr(CSDN->getValueAPF());
} else if (const GlobalAddressSDNode *GADN =

40
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -900,7 +900,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
case ISD::SHL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
SDValue InOp = Op.getOperand(0);
// If the shift count is an invalid immediate, don't do anything.
@ -913,7 +913,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (InOp.getOpcode() == ISD::SRL &&
isa<ConstantSDNode>(InOp.getOperand(1))) {
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
unsigned Opc = ISD::SHL;
int Diff = ShAmt-C1;
if (Diff < 0) {
@ -932,16 +932,16 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
KnownZero, KnownOne, TLO, Depth+1))
return true;
KnownZero <<= SA->getValue();
KnownOne <<= SA->getValue();
KnownZero <<= SA->getZExtValue();
KnownOne <<= SA->getZExtValue();
// low bits known zero.
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue());
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
}
break;
case ISD::SRL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
unsigned VTSize = VT.getSizeInBits();
SDValue InOp = Op.getOperand(0);
@ -955,7 +955,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (InOp.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(InOp.getOperand(1))) {
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
unsigned Opc = ISD::SRL;
int Diff = ShAmt-C1;
if (Diff < 0) {
@ -985,7 +985,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
case ISD::SRA:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
MVT VT = Op.getValueType();
unsigned ShAmt = SA->getValue();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
@ -1162,10 +1162,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
APInt HighBits = APInt::getHighBitsSet(InBitWidth,
InBitWidth - BitWidth);
HighBits = HighBits.lshr(ShAmt->getValue());
HighBits = HighBits.lshr(ShAmt->getZExtValue());
HighBits.trunc(BitWidth);
if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) {
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
// None of the shifted in bits are needed. Add a truncate of the
// shift input, then shift it.
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
@ -1290,7 +1290,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
@ -1389,7 +1389,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
if (N0.getOpcode() == ISD::SETCC) {
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
if (TrueWhenTrue)
return N0;
@ -1498,12 +1498,12 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
if (isPowerOf2_64(AndRHS->getValue())) {
if (isPowerOf2_64(AndRHS->getZExtValue())) {
return DAG.getNode(ISD::SRL, VT, N0,
DAG.getConstant(Log2_64(AndRHS->getValue()),
DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
getShiftAmountTy()));
}
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C1 is a single bit.
if (C1.isPowerOf2()) {
@ -1586,7 +1586,8 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
// Turn (X+C1) == C2 --> X == C2-C1
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
return DAG.getSetCC(VT, N0.getOperand(0),
DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
DAG.getConstant(RHSC->getAPIntValue()-
LHSR->getAPIntValue(),
N0.getValueType()), Cond);
}
@ -1878,7 +1879,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
if (GA) { // Either &GV or &GV+C
if (ConstraintLetter != 'n') {
int64_t Offs = GA->getOffset();
if (C) Offs += C->getValue();
if (C) Offs += C->getZExtValue();
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Op.getValueType(), Offs));
return;
@ -1887,7 +1888,8 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
if (C) { // just C, no GV.
// Simple constants are not allowed for 's'.
if (ConstraintLetter != 's') {
Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(),
Op.getValueType()));
return;
}
}
@ -2336,7 +2338,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
return SDValue(); // BuildUDIV only operates on i32 or i64
uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
// Multiply the numerator (operand 0) by the magic value

48
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -104,7 +104,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
if (N.getOpcode() == ISD::MUL) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// X * [3,5,9] -> X + X * [2,4,8] etc.
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if (RHSC & 1) {
RHSC = RHSC & ~1;
ARM_AM::AddrOpc AddSub = ARM_AM::add;
@ -142,7 +142,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
// Match simple R +/- imm12 operands.
if (N.getOpcode() == ISD::ADD)
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if ((RHSC >= 0 && RHSC < 0x1000) ||
(RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
Base = N.getOperand(0);
@ -177,7 +177,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
// it.
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
ShAmt = Sh->getValue();
ShAmt = Sh->getZExtValue();
Offset = N.getOperand(1).getOperand(0);
} else {
ShOpcVal = ARM_AM::no_shift;
@ -192,7 +192,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
// fold it.
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
ShAmt = Sh->getValue();
ShAmt = Sh->getZExtValue();
Offset = N.getOperand(0).getOperand(0);
Base = N.getOperand(1);
} else {
@ -215,7 +215,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
? ARM_AM::add : ARM_AM::sub;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getValue();
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 0x1000) { // 12 bits.
Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
@ -232,7 +232,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
// Check to see if the RHS of the shift is a constant, if not, we can't fold
// it.
if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
ShAmt = Sh->getValue();
ShAmt = Sh->getZExtValue();
Offset = N.getOperand(0);
} else {
ShOpcVal = ARM_AM::no_shift;
@ -269,7 +269,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
// If the RHS is +/- imm8, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if ((RHSC >= 0 && RHSC < 256) ||
(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
Base = N.getOperand(0);
@ -304,7 +304,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
? ARM_AM::add : ARM_AM::sub;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getValue();
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 256) {
Offset = CurDAG->getRegister(0, MVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
@ -335,7 +335,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
// If the RHS is +/- imm8, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
RHSC >>= 2;
if ((RHSC >= 0 && RHSC < 256) ||
@ -369,7 +369,7 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
Offset = N.getOperand(0);
SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i32);
return true;
}
@ -426,7 +426,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
// If the RHS is + imm5 * scale, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
RHSC /= Scale;
if (RHSC >= 0 && RHSC < 32) {
@ -479,7 +479,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
(LHSR && LHSR->getReg() == ARM::SP)) {
// If the RHS is + imm8 * scale, fold into addr mode.
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
RHSC >>= 2;
if (RHSC >= 0 && RHSC < 256) {
@ -513,7 +513,7 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
ShReg = CurDAG->getRegister(0, MVT::i32);
ShImmVal = RHS->getValue() & 31;
ShImmVal = RHS->getZExtValue() & 31;
} else {
ShReg = N.getOperand(1);
}
@ -537,7 +537,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
switch (N->getOpcode()) {
default: break;
case ISD::Constant: {
unsigned Val = cast<ConstantSDNode>(N)->getValue();
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
bool UseCP = true;
if (Subtarget->isThumb())
UseCP = (Val > 255 && // MOV
@ -609,7 +609,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
if (Subtarget->isThumb())
break;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
unsigned RHSV = C->getValue();
unsigned RHSV = C->getZExtValue();
if (!RHSV) break;
if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
SDValue V = Op.getOperand(0);
@ -725,7 +725,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
@ -761,7 +762,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(CPTmp2);
AddToISelQueue(InFlag);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
}
@ -778,10 +780,12 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(N0);
AddToISelQueue(InFlag);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
cast<ConstantSDNode>(N1)->getZExtValue()),
MVT::i32);
Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
}
@ -799,7 +803,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
@ -831,7 +836,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(N1);
AddToISelQueue(InFlag);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {

16
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -412,7 +412,7 @@ HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
MVT RetVT= Op.getNode()->getValueType(0);
SDValue Chain = Op.getOperand(0);
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
assert((CallConv == CallingConv::C ||
CallConv == CallingConv::Fast) && "unknown calling convention");
SDValue Callee = Op.getOperand(4);
@ -903,7 +903,7 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
@ -995,7 +995,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
NumGPRs, ArgOffset));
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
if (isVarArg) {
static const unsigned GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
@ -1068,7 +1068,7 @@ static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getValue();
unsigned C = RHSC->getZExtValue();
if (!isLegalCmpImmediate(C, isThumb)) {
// Constant does not fit, try adjusting it by one?
switch (CC) {
@ -1270,7 +1270,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
return SDValue();
uint64_t SizeVal = ConstantSize->getValue();
uint64_t SizeVal = ConstantSize->getZExtValue();
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
return SDValue();
@ -1381,7 +1381,7 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
// We only lower SRA, SRL of 1 here, all others use generic lowering.
if (!isa<ConstantSDNode>(N->getOperand(1)) ||
cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
return 0;
// If we are in thumb mode, we don't have RRX.
@ -1673,7 +1673,7 @@ static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
// AddressingMode 3
Base = Ptr->getOperand(0);
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if (RHSC < 0 && RHSC > -256) {
isInc = false;
Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
@ -1686,7 +1686,7 @@ static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
} else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
// AddressingMode 2
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
int RHSC = (int)RHS->getValue();
int RHSC = (int)RHS->getZExtValue();
if (RHSC < 0 && RHSC > -0x1000) {
isInc = false;
Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));

33
lib/Target/ARM/ARMInstrInfo.td
View File

@ -108,47 +108,49 @@ class RegConstraint<string C> {
// so_imm_XFORM - Return a so_imm value packed into the format described for
// so_imm def below.
def so_imm_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
MVT::i32);
}]>;
// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
// so_imm_neg def below.
def so_imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
MVT::i32);
}]>;
// so_imm_not_XFORM - Return a so_imm value packed into the format described for
// so_imm_not def below.
def so_imm_not_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
MVT::i32);
}]>;
// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
def rot_imm : PatLeaf<(i32 imm), [{
int32_t v = (int32_t)N->getValue();
int32_t v = (int32_t)N->getZExtValue();
return v == 8 || v == 16 || v == 24;
}]>;
/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
def imm1_15 : PatLeaf<(i32 imm), [{
return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
}]>;
/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
def imm16_31 : PatLeaf<(i32 imm), [{
return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
}]>;
def so_imm_neg :
PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
so_imm_neg_XFORM>;
PatLeaf<(imm), [{
return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
}], so_imm_neg_XFORM>;
def so_imm_not :
PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
so_imm_not_XFORM>;
PatLeaf<(imm), [{
return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
}], so_imm_not_XFORM>;
// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
def sext_16_node : PatLeaf<(i32 GPR:$a), [{
@ -199,7 +201,7 @@ def so_reg : Operand<i32>, // reg reg imm
// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
def so_imm : Operand<i32>,
PatLeaf<(imm),
[{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
[{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
so_imm_XFORM> {
let PrintMethod = "printSOImmOperand";
}
@ -208,18 +210,19 @@ def so_imm : Operand<i32>,
// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
// get the first/second pieces.
def so_imm2part : Operand<i32>,
PatLeaf<(imm),
[{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
PatLeaf<(imm), [{
return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
}]> {
let PrintMethod = "printSOImm2PartOperand";
}
def so_imm2part_1 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
}]>;
def so_imm2part_2 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
}]>;

22
lib/Target/ARM/ARMInstrThumb.td
View File

@ -19,33 +19,33 @@ def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
def imm_comp_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;
/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
def imm0_7 : PatLeaf<(i32 imm), [{
return (uint32_t)N->getValue() < 8;
return (uint32_t)N->getZExtValue() < 8;
}]>;
def imm0_7_neg : PatLeaf<(i32 imm), [{
return (uint32_t)-N->getValue() < 8;
return (uint32_t)-N->getZExtValue() < 8;
}], imm_neg_XFORM>;
def imm0_255 : PatLeaf<(i32 imm), [{
return (uint32_t)N->getValue() < 256;
return (uint32_t)N->getZExtValue() < 256;
}]>;
def imm0_255_comp : PatLeaf<(i32 imm), [{
return ~((uint32_t)N->getValue()) < 256;
return ~((uint32_t)N->getZExtValue()) < 256;
}]>;
def imm8_255 : PatLeaf<(i32 imm), [{
return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
}]>;
def imm8_255_neg : PatLeaf<(i32 imm), [{
unsigned Val = -N->getValue();
unsigned Val = -N->getZExtValue();
return Val >= 8 && Val < 256;
}], imm_neg_XFORM>;
@ -53,16 +53,16 @@ def imm8_255_neg : PatLeaf<(i32 imm), [{
// This uses thumb_immshifted to match and thumb_immshifted_val and
// thumb_immshifted_shamt to get the val/shift pieces.
def thumb_immshifted : PatLeaf<(imm), [{
return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
}]>;
def thumb_immshifted_val : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(V, MVT::i32);
}]>;
def thumb_immshifted_shamt : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
return CurDAG->getTargetConstant(V, MVT::i32);
}]>;

6
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -300,7 +300,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
}
case ISD::Constant: {
uint64_t uval = cast<ConstantSDNode>(N)->getValue();
uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
if (uval == 0) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
@ -426,8 +426,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
if (N->getOperand(0).getOpcode() == ISD::SRL &&
(MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
(SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
uint64_t sval = SC->getValue();
uint64_t mval = MC->getValue();
uint64_t sval = SC->getZExtValue();
uint64_t mval = MC->getZExtValue();
// If the result is a zap, let the autogened stuff handle it.
if (get_zapImm(N->getOperand(0), mval))
break;

2
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -264,7 +264,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
}
// If the functions takes variable number of arguments, copy all regs to stack
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
if (isVarArg) {
VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
std::vector<SDValue> LS;

71
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -43,54 +43,58 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeqEnd,
//Paterns for matching
//********************
def invX : SDNodeXForm<imm, [{ //invert
return getI64Imm(~N->getValue());
return getI64Imm(~N->getZExtValue());
}]>;
def negX : SDNodeXForm<imm, [{ //negate
return getI64Imm(~N->getValue() + 1);
return getI64Imm(~N->getZExtValue() + 1);
}]>;
def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
return getI64Imm(((int64_t)N->getValue() << 32) >> 32);
return getI64Imm(((int64_t)N->getZExtValue() << 32) >> 32);
}]>;
def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
return getI64Imm(((int64_t)N->getValue() << 48) >> 48);
return getI64Imm(((int64_t)N->getZExtValue() << 48) >> 48);
}]>;
def LL16 : SDNodeXForm<imm, [{ //lda part of constant
return getI64Imm(get_lda16(N->getValue()));
return getI64Imm(get_lda16(N->getZExtValue()));
}]>;
def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
return getI64Imm(get_ldah16(N->getValue()));
return getI64Imm(get_ldah16(N->getZExtValue()));
}]>;
def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi
ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
return getI64Imm(get_zapImm(SDValue(), RHS->getValue()));
return getI64Imm(get_zapImm(SDValue(), RHS->getZExtValue()));
}]>;
def nearP2X : SDNodeXForm<imm, [{
return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getZExtValue())));
}]>;
def nearP2RemX : SDNodeXForm<imm, [{
uint64_t x = abs(N->getValue() - getNearPower2((uint64_t)N->getValue()));
uint64_t x =
abs(N->getZExtValue() - getNearPower2((uint64_t)N->getZExtValue()));
return getI64Imm(Log2_64(x));
}]>;
def immUExt8 : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
return (uint64_t)N->getValue() == (uint8_t)N->getValue();
return (uint64_t)N->getZExtValue() == (uint8_t)N->getZExtValue();
}]>;
def immUExt8inv : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
return (uint64_t)~N->getZExtValue() == (uint8_t)~N->getZExtValue();
}], invX>;
def immUExt8neg : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1);
return ((uint64_t)~N->getZExtValue() + 1) ==
(uint8_t)((uint64_t)~N->getZExtValue() + 1);
}], negX>;
def immSExt16 : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue();
return ((int64_t)N->getZExtValue() << 48) >> 48 ==
(int64_t)N->getZExtValue();
}]>;
def immSExt16int : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32;
return ((int64_t)N->getZExtValue() << 48) >> 48 ==
((int64_t)N->getZExtValue() << 32) >> 32;
}], SExt16>;
def zappat : PatFrag<(ops node:$LHS), (and node:$LHS, imm:$L), [{
ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getValue());
uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getZExtValue());
return build != 0;
}]>;
@ -99,29 +103,32 @@ def immFPZ : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
return true;
}]>;
def immRem1 : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),1, 0);}]>;
def immRem2 : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),2, 0);}]>;
def immRem3 : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),3, 0);}]>;
def immRem4 : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),4, 0);}]>;
def immRem5 : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),5, 0);}]>;
def immRem1n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),1, 1);}]>;
def immRem2n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),2, 1);}]>;
def immRem3n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),3, 1);}]>;
def immRem4n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),4, 1);}]>;
def immRem5n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),5, 1);}]>;
def immRem1 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),1,0);}]>;
def immRem2 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),2,0);}]>;
def immRem3 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),3,0);}]>;
def immRem4 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),4,0);}]>;
def immRem5 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),5,0);}]>;
def immRem1n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),1,1);}]>;
def immRem2n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),2,1);}]>;
def immRem3n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),3,1);}]>;
def immRem4n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),4,1);}]>;
def immRem5n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),5,1);}]>;
def immRemP2n : PatLeaf<(imm), [{
return isPowerOf2_64(getNearPower2((uint64_t)N->getValue()) - N->getValue());
return isPowerOf2_64(getNearPower2((uint64_t)N->getZExtValue()) -
N->getZExtValue());
}]>;
def immRemP2 : PatLeaf<(imm), [{
return isPowerOf2_64(N->getValue() - getNearPower2((uint64_t)N->getValue()));
return isPowerOf2_64(N->getZExtValue() -
getNearPower2((uint64_t)N->getZExtValue()));
}]>;
def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
int64_t d = abs((int64_t)N->getValue() - (int64_t)getNearPower2((uint64_t)N->getValue()));
int64_t d = abs((int64_t)N->getZExtValue() -
(int64_t)getNearPower2((uint64_t)N->getZExtValue()));
if (isPowerOf2_64(d)) return false;
switch (d) {
case 1: case 3: case 5: return false;
default: return (uint64_t)N->getValue() == (uint8_t)N->getValue();
default: return (uint64_t)N->getZExtValue() == (uint8_t)N->getZExtValue();
};
}]>;
@ -848,7 +855,7 @@ def FBNE : br_fcc<0x36, "fbne">;
//An ugly trick to get the opcode as an imm I can use
def immBRCond : SDNodeXForm<imm, [{
switch((uint64_t)N->getValue()) {
switch((uint64_t)N->getZExtValue()) {
case 0: return getI64Imm(Alpha::BEQ);
case 1: return getI64Imm(Alpha::BNE);
case 2: return getI64Imm(Alpha::BGE);
@ -1020,12 +1027,12 @@ def : Pat<(brcond (setune F8RC:$RA, immFPZ), bb:$DISP),
def immConst2Part : PatLeaf<(imm), [{
//true if imm fits in a LDAH LDA pair
int64_t val = (int64_t)N->getValue();
int64_t val = (int64_t)N->getZExtValue();
return (val <= IMM_FULLHIGH && val >= IMM_FULLLOW);
}]>;
def immConst2PartInt : PatLeaf<(imm), [{
//true if imm fits in a LDAH LDA pair with zeroext
uint64_t uval = N->getValue();
uint64_t uval = N->getZExtValue();
int32_t val32 = (int32_t)uval;
return ((uval >> 32) == 0 && //empty upper bits
val32 <= IMM_FULLHIGH);

10
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -87,7 +87,7 @@ namespace {
bool
isI16IntU10Immediate(ConstantSDNode *CN)
{
return isU10Constant((short) CN->getValue());
return isU10Constant((short) CN->getZExtValue());
}
//! SDNode predicate for i16 sign-extended, 10-bit immediate values
@ -111,15 +111,15 @@ namespace {
isIntS16Immediate(ConstantSDNode *CN, short &Imm)
{
MVT vt = CN->getValueType(0);
Imm = (short) CN->getValue();
Imm = (short) CN->getZExtValue();
if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
return true;
} else if (vt == MVT::i32) {
int32_t i_val = (int32_t) CN->getValue();
int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
} else {
int64_t i_val = (int64_t) CN->getValue();
int64_t i_val = (int64_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
}
@ -676,7 +676,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
if (Op1.getOpcode() == ISD::Constant) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
Op1 = CurDAG->getTargetConstant(CN->getZExtValue(), VT);
NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
AddToISelQueue(Op0);
AddToISelQueue(Op1);

92
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -524,7 +524,7 @@ AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
|| Op1.getOpcode() == ISD::TargetConstant) {
const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
alignOffs = (int) CN->getValue();
alignOffs = (int) CN->getZExtValue();
prefSlotOffs = (int) (alignOffs & 0xf);
// Adjust the rotation amount to ensure that the final result ends up in
@ -880,7 +880,7 @@ LowerConstant(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
if (VT == MVT::i64) {
SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
SDValue T = DAG.getConstant(CN->getZExtValue(), MVT::i64);
return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
} else {
@ -938,7 +938,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
MachineRegisterInfo &RegInfo = MF.getRegInfo();
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
@ -1090,12 +1090,12 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return 0;
int Addr = C->getValue();
int Addr = C->getZExtValue();
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
(Addr << 14 >> 14) != Addr)
return 0; // Top 14 bits have to be sext of immediate.
return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).getNode();
return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
}
static
@ -1103,8 +1103,8 @@ SDValue
LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
SDValue Chain = Op.getOperand(0);
#if 0
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue() != 0;
#endif
SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
@ -1379,9 +1379,9 @@ getVecImm(SDNode *N) {
SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
uint64_t Value = CN->getZExtValue();
if (ValueType == MVT::i64) {
uint64_t UValue = CN->getValue();
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
@ -1403,7 +1403,7 @@ SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
if (ValueType == MVT::i64) {
uint64_t UValue = CN->getValue();
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
@ -1426,7 +1426,7 @@ SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSignExtended();
if (ValueType == MVT::i64) {
uint64_t UValue = CN->getValue();
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
if (upper != lower)
@ -1450,7 +1450,7 @@ SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getValue();
int Value = (int) CN->getZExtValue();
if (ValueType == MVT::i16
&& Value <= 0xffff /* truncated from uint64_t */
&& ((short) Value >> 8) == ((short) Value & 0xff))
@ -1469,7 +1469,7 @@ SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
MVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getValue();
uint64_t Value = CN->getZExtValue();
if ((ValueType == MVT::i32
&& ((unsigned) Value & 0xffff0000) == (unsigned) Value)
|| (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
@ -1482,7 +1482,7 @@ SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
/// get_v4i32_imm - Catch-all for general 32-bit constant vectors
SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
return DAG.getConstant((unsigned) CN->getValue(), MVT::i32);
return DAG.getConstant((unsigned) CN->getZExtValue(), MVT::i32);
}
return SDValue();
@ -1491,7 +1491,7 @@ SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
/// get_v4i32_imm - Catch-all for general 64-bit constant vectors
SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
return DAG.getConstant((unsigned) CN->getValue(), MVT::i64);
return DAG.getConstant((unsigned) CN->getZExtValue(), MVT::i64);
}
return SDValue();
@ -1520,7 +1520,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
continue;
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
EltBits = CN->getValue() & (~0ULL >> (64-EltBitSize));
EltBits = CN->getZExtValue() & (~0ULL >> (64-EltBitSize));
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
const APFloat &apf = CN->getValueAPF();
EltBits = (CN->getValueType(0) == MVT::f32
@ -1807,7 +1807,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
SrcElt = 0;
else
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
if (SrcElt >= V2EltIdx0) {
++EltsFromV2;
@ -1846,7 +1846,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
SrcElt = 0;
else
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
for (unsigned j = 0; j < BytesPerElement; ++j) {
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
@ -1884,7 +1884,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
}
SDValue CValue = DAG.getConstant(CN->getValue(), VT);
SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
for (size_t j = 0; j < n_copies; ++j)
ConstVecValues.push_back(CValue);
@ -2101,7 +2101,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
assert(C != 0 && "LowerEXTRACT_VECTOR_ELT expecting constant SDNode");
int EltNo = (int) C->getValue();
int EltNo = (int) C->getZExtValue();
// sanity checks:
if (VT == MVT::i8 && EltNo >= 16)
@ -2193,7 +2193,7 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
DAG.getNode(SPUISD::INSERT_MASK, VT,
DAG.getNode(ISD::ADD, PtrVT,
PtrBase,
DAG.getConstant(CN->getValue(),
DAG.getConstant(CN->getZExtValue(),
PtrVT))));
return result;
@ -2215,10 +2215,12 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
SDValue N1 = Op.getOperand(1);
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i16));
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
DAG.getNode(Opc, MVT::i16, N0, N1));
}
@ -2228,13 +2230,15 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i16));
SDValue ExpandArg =
DAG.getNode(ISD::OR, MVT::i16, N0,
DAG.getNode(ISD::SHL, MVT::i16,
@ -2248,13 +2252,15 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i16));
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
DAG.getNode(Opc, MVT::i16, N0, N1));
}
@ -2263,13 +2269,15 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16)
? ISD::SIGN_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i16));
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
DAG.getNode(Opc, MVT::i16, N0, N1));
}
@ -2278,11 +2286,13 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc)
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
? DAG.getNode(N1Opc, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
MVT::i16));
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
DAG.getNode(Opc, MVT::i16, N0, N1));
break;
@ -2780,13 +2790,13 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
ConstantSDNode *CN0 = cast<ConstantSDNode>(Op1);
ConstantSDNode *CN1 = cast<ConstantSDNode>(Op01);
SDValue combinedConst =
DAG.getConstant(CN0->getValue() + CN1->getValue(),
DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(),
Op0.getValueType());
DEBUG(cerr << "Replace: (add " << CN0->getValue() << ", "
<< "(SPUindirect <arg>, " << CN1->getValue() << "))\n");
DEBUG(cerr << "Replace: (add " << CN0->getZExtValue() << ", "
<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n");
DEBUG(cerr << "With: (SPUindirect <arg>, "
<< CN0->getValue() + CN1->getValue() << ")\n");
<< CN0->getZExtValue() + CN1->getZExtValue() << ")\n");
return DAG.getNode(SPUISD::IndirectAddr, Op0.getValueType(),
Op0.getOperand(0), combinedConst);
}
@ -2800,13 +2810,13 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
ConstantSDNode *CN0 = cast<ConstantSDNode>(Op0);
ConstantSDNode *CN1 = cast<ConstantSDNode>(Op11);
SDValue combinedConst =
DAG.getConstant(CN0->getValue() + CN1->getValue(),
DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(),
Op0.getValueType());
DEBUG(cerr << "Replace: (add " << CN0->getValue() << ", "
<< "(SPUindirect <arg>, " << CN1->getValue() << "))\n");
DEBUG(cerr << "Replace: (add " << CN0->getZExtValue() << ", "
<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n");
DEBUG(cerr << "With: (SPUindirect <arg>, "
<< CN0->getValue() + CN1->getValue() << ")\n");
<< CN0->getZExtValue() + CN1->getZExtValue() << ")\n");
return DAG.getNode(SPUISD::IndirectAddr, Op1.getValueType(),
Op1.getOperand(0), combinedConst);
@ -2835,7 +2845,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
case SPUISD::IndirectAddr: {
if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(1));
if (CN->getValue() == 0) {
if (CN->getZExtValue() == 0) {
// (SPUindirect (SPUaform <addr>, 0), 0) ->
// (SPUaform <addr>, 0)
@ -2863,7 +2873,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
// Kill degenerate vector shifts:
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
if (CN->getValue() == 0) {
if (CN->getZExtValue() == 0) {
Result = Op0;
}
}

26
lib/Target/CellSPU/SPUOperands.td
View File

@ -10,7 +10,7 @@
//===----------------------------------------------------------------------===//
def LO16 : SDNodeXForm<imm, [{
unsigned val = N->getValue();
unsigned val = N->getZExtValue();
// Transformation function: get the low 16 bits.
return getI32Imm(val & 0xffff);
}]>;
@ -33,12 +33,12 @@ def LO16_vec : SDNodeXForm<scalar_to_vector, [{
assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
return getI32Imm((unsigned)CN->getValue() & 0xffff);
return getI32Imm((unsigned)CN->getZExtValue() & 0xffff);
}]>;
// Transform an immediate, returning the high 16 bits shifted down:
def HI16 : SDNodeXForm<imm, [{
return getI32Imm((unsigned)N->getValue() >> 16);
return getI32Imm((unsigned)N->getZExtValue() >> 16);
}]>;
// Transformation function: shift the high 16 bit immediate from a build_vector
@ -59,7 +59,7 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
return getI32Imm((unsigned)CN->getValue() >> 16);
return getI32Imm((unsigned)CN->getZExtValue() >> 16);
}]>;
// simm7 predicate - True if the immediate fits in an 7-bit signed
@ -72,7 +72,7 @@ def simm7: PatLeaf<(imm), [{
// uimm7 predicate - True if the immediate fits in an 7-bit unsigned
// field.
def uimm7: PatLeaf<(imm), [{
return (N->getValue() <= 0x7f);
return (N->getZExtValue() <= 0x7f);
}]>;
// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
@ -84,7 +84,7 @@ def immSExt8 : PatLeaf<(imm), [{
// immU8: immediate, unsigned 8-bit quantity
def immU8 : PatLeaf<(imm), [{
return (N->getValue() <= 0xff);
return (N->getZExtValue() <= 0xff);
}]>;
// i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
@ -127,17 +127,17 @@ def immSExt16 : PatLeaf<(imm), [{
def immZExt16 : PatLeaf<(imm), [{
// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
// field.
return (uint64_t)N->getValue() == (unsigned short)N->getValue();
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>;
def immU16 : PatLeaf<(imm), [{
// immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
return (uint64_t)N->getZExtValue() == (N->getZExtValue() & 0xffff);
}]>;
def imm18 : PatLeaf<(imm), [{
// imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
int Value = (int) N->getValue();
int Value = (int) N->getZExtValue();
return ((Value & ((1 << 19) - 1)) == Value);
}]>;
@ -145,7 +145,7 @@ def lo16 : PatLeaf<(imm), [{
// lo16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
if (N->getValueType(0) == MVT::i32) {
uint32_t val = N->getValue();
uint32_t val = N->getZExtValue();
return ((val & 0x0000ffff) == val);
}
@ -156,10 +156,10 @@ def hi16 : PatLeaf<(imm), [{
// hi16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
if (N->getValueType(0) == MVT::i32) {
uint32_t val = uint32_t(N->getValue());
uint32_t val = uint32_t(N->getZExtValue());
return ((val & 0xffff0000) == val);
} else if (N->getValueType(0) == MVT::i64) {
uint64_t val = N->getValue();
uint64_t val = N->getZExtValue();
return ((val & 0xffff0000ULL) == val);
}
@ -169,7 +169,7 @@ def hi16 : PatLeaf<(imm), [{
def bitshift : PatLeaf<(imm), [{
// bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
// (shift left quadword by bits immediate)
int64_t Val = N->getValue();
int64_t Val = N->getZExtValue();
return (Val > 0 && Val <= 7);
}]>;

2
lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -560,7 +560,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: {
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDValue N0 = N->getOperand(0);

18
lib/Target/IA64/IA64InstrInfo.td
View File

@ -66,7 +66,7 @@ let PrintMethod = "printCallOperand" in
def is32ones : PatLeaf<(i64 imm), [{
// is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
// Used to create ZXT4s appropriately
uint64_t v = (uint64_t)N->getValue();
uint64_t v = (uint64_t)N->getZExtValue();
return (v == 0x00000000FFFFFFFFLL);
}]>;
@ -75,36 +75,36 @@ def is32ones : PatLeaf<(i64 imm), [{
// etc, through 0x00000000FFFFFFFF
// Used to test for the suitability of mix*
def isMIX1Lable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
return((uint64_t)N->getZExtValue()==0xFF00FF00FF00FF00LL);
}]>;
def isMIX1Rable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
return((uint64_t)N->getZExtValue()==0x00FF00FF00FF00FFLL);
}]>;
def isMIX2Lable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
return((uint64_t)N->getZExtValue()==0xFFFF0000FFFF0000LL);
}]>;
def isMIX2Rable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
return((uint64_t)N->getZExtValue()==0x0000FFFF0000FFFFLL);
}]>;
def isMIX4Lable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
return((uint64_t)N->getZExtValue()==0xFFFFFFFF00000000LL);
}]>;
def isMIX4Rable: PatLeaf<(i64 imm), [{
return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
return((uint64_t)N->getZExtValue()==0x00000000FFFFFFFFLL);
}]>;
def isSHLADDimm: PatLeaf<(i64 imm), [{
// isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
// - 0 is *not* okay.
// Used to create shladd instructions appropriately
int64_t v = (int64_t)N->getValue();
int64_t v = (int64_t)N->getZExtValue();
return (v >= 1 && v <= 4);
}]>;
def immSExt14 : PatLeaf<(i64 imm), [{
// immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
// field. Used by instructions like 'adds'.
int64_t v = (int64_t)N->getValue();
int64_t v = (int64_t)N->getZExtValue();
return (v <= 8191 && v >= -8192);
}]>;

2
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -177,7 +177,7 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
Base = Addr.getOperand(0);
}
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}

10
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -421,7 +421,8 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG)
SDValue CondRes = Op.getOperand(1);
SDValue CCNode = CondRes.getOperand(2);
Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
@ -586,7 +587,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG)
SDValue Chain = Op.getOperand(0);
SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -762,7 +763,8 @@ SDNode *MipsTargetLowering::
LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
bool isVarArg =
cast<ConstantSDNode>(TheCall->getOperand(2))->getZExtValue() != 0;
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
@ -802,7 +804,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);

14
lib/Target/Mips/MipsInstrInfo.td
View File

@ -85,21 +85,21 @@ def mem : Operand<i32> {
// Transformation Function - get the lower 16 bits.
def LO16 : SDNodeXForm<imm, [{
return getI32Imm((unsigned)N->getValue() & 0xFFFF);
return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
}]>;
// Transformation Function - get the higher 16 bits.
def HI16 : SDNodeXForm<imm, [{
return getI32Imm((unsigned)N->getValue() >> 16);
return getI32Imm((unsigned)N->getZExtValue() >> 16);
}]>;
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{
if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getValue() == (short)N->getValue();
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getValue() == (short)N->getValue();
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
}]>;
// Node immediate fits as 16-bit zero extended on target immediate.
@ -108,14 +108,14 @@ def immSExt16 : PatLeaf<(imm), [{
// e.g. addiu, sltiu
def immZExt16 : PatLeaf<(imm), [{
if (N->getValueType(0) == MVT::i32)
return (uint32_t)N->getValue() == (unsigned short)N->getValue();
return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
else
return (uint64_t)N->getValue() == (unsigned short)N->getValue();
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>;
// shamt field must fit in 5 bits.
def immZExt5 : PatLeaf<(imm), [{
return N->getValue() == ((N->getValue()) & 0x1f) ;
return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
}]>;
// Mips Address Mode! SDNode frameindex could possibily be a match

5
lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
View File

@ -141,10 +141,11 @@ SelectDirectAM (SDValue Op, SDValue N, SDValue &Base, SDValue &Offset)
if (N.getOpcode() == ISD::ADD) {
GC = dyn_cast<ConstantSDNode>(N.getOperand(1));
Offset = CurDAG->getTargetConstant((unsigned char)GC->getValue(), MVT::i8);
Offset = CurDAG->getTargetConstant((unsigned char)GC->getZExtValue(),
MVT::i8);
if ((GA = dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))) {
Base = CurDAG->getTargetGlobalAddress(GA->getGlobal(), MVT::i16,
GC->getValue());
GC->getZExtValue());
return true;
}
else if (FrameIndexSDNode *FIN

14
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -390,7 +390,8 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
InOp[1].getOpcode() == ISD::Constant) {
ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16);
return DAG.getConstant(CST0->getZExtValue() + CST1->getZExtValue(),
MVT::i16);
}
break;
@ -406,7 +407,8 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
InOp[1].getOpcode() == ISD::Constant) {
ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16);
return DAG.getConstant(CST0->getZExtValue() - CST1->getZExtValue(),
MVT::i16);
}
break;
@ -432,8 +434,8 @@ PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
else if (InOp[i].getOpcode() == ISD::Constant) {
changed = true;
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(InOp[i]);
LoOps[i] = DAG.getConstant(CST->getValue() & 0xFF, MVT::i8);
HiOps[i] = DAG.getConstant(CST->getValue() >> 8, MVT::i8);
LoOps[i] = DAG.getConstant(CST->getZExtValue() & 0xFF, MVT::i8);
HiOps[i] = DAG.getConstant(CST->getZExtValue() >> 8, MVT::i8);
}
else if (InOp[i].getOpcode() == PIC16ISD::Package) {
LoOps[i] = InOp[i].getOperand(0);
@ -670,7 +672,7 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
//create direct addressing a = CONST
CST = dyn_cast<ConstantSDNode>(Src);
for (i = 0; i < NUM_STORES; i++) {
SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDValue CNST = DAG.getConstant(CST->getZExtValue() >> i*8, MVT::i8);
SDValue ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
DAG.getConstant(DstOff, MVT::i16));
Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
@ -690,7 +692,7 @@ SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
Chain = Load.getValue(1);
for (i=0; i<NUM_STORES; i++) {
SDValue CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
SDValue CNST = DAG.getConstant(CST->getZExtValue() >> i*8, MVT::i8);
Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
Chain = Stores[i];
DstOff += 1;

2
lib/Target/PIC16/PIC16InstrInfo.td
View File

@ -51,7 +51,7 @@ def PIC16Wrapper : SDNode<"PIC16ISD::Wrapper", SDTIntUnaryOp>;
// so_imm_XFORM - Return a so_imm value packed into the format described for
// so_imm def below.
def so_imm_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((int8_t)N->getValue(), MVT::i32);
return CurDAG->getTargetConstant((int8_t)N->getZExtValue(), MVT::i32);
}]>;
def so_imm : Operand<i8>,

4
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -101,8 +101,8 @@ isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
// Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
// to see if the load and store actually overlap.
int StoreOffs = StoreOffset->getValue();
int LoadOffs = LoadOffset->getValue();
int StoreOffs = StoreOffset->getZExtValue();
int LoadOffs = LoadOffset->getZExtValue();
if (StoreOffs < LoadOffs) {
if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
} else {

16
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -306,11 +306,11 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) {
if (N->getOpcode() != ISD::Constant)
return false;
Imm = (short)cast<ConstantSDNode>(N)->getValue();
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
}
static bool isIntS16Immediate(SDValue Op, short &Imm) {
@ -322,7 +322,7 @@ static bool isIntS16Immediate(SDValue Op, short &Imm) {
/// operand. If so Imm will receive the 32-bit value.
static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
Imm = cast<ConstantSDNode>(N)->getValue();
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
return false;
@ -332,7 +332,7 @@ static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
/// operand. If so Imm will receive the 64-bit value.
static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
Imm = cast<ConstantSDNode>(N)->getValue();
Imm = cast<ConstantSDNode>(N)->getZExtValue();
return true;
}
return false;
@ -785,7 +785,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
case ISD::Constant: {
if (N->getValueType(0) == MVT::i64) {
// Get 64 bit value.
int64_t Imm = cast<ConstantSDNode>(N)->getValue();
int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
// Assume no remaining bits.
unsigned Remainder = 0;
// Assume no shift required.
@ -1059,7 +1059,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
if (N1C->isNullValue() && N3C->isNullValue() &&
N2C->getValue() == 1ULL && CC == ISD::SETNE &&
N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
// FIXME: Implement this optzn for PPC64.
N->getValueType(0) == MVT::i32) {
AddToISelQueue(N->getOperand(0));
@ -1100,7 +1100,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
// Prevent PPC::PRED_* from being selected into LI.
SDValue Pred =
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);

84
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -452,7 +452,7 @@ static bool isFloatingPointZero(SDValue Op) {
/// true if Op is undef or if it matches the specified value.
static bool isConstantOrUndef(SDValue Op, unsigned Val) {
return Op.getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(Op)->getValue() == Val;
cast<ConstantSDNode>(Op)->getZExtValue() == Val;
}
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
@ -541,7 +541,7 @@ int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
// Otherwise, check to see if the rest of the elements are consequtively
// numbered from this value.
unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
if (ShiftAmt < i) return -1;
ShiftAmt -= i;
@ -573,17 +573,17 @@ bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
unsigned ElementBase = 0;
SDValue Elt = N->getOperand(0);
if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
ElementBase = EltV->getValue();
ElementBase = EltV->getZExtValue();
else
return false; // FIXME: Handle UNDEF elements too!
if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
return false;
// Check that they are consequtive.
for (unsigned i = 1; i != EltSize; ++i) {
if (!isa<ConstantSDNode>(N->getOperand(i)) ||
cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
return false;
}
@ -614,7 +614,7 @@ bool PPC::isAllNegativeZeroVector(SDNode *N) {
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
assert(isSplatShuffleMask(N, EltSize));
return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
}
/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
@ -665,7 +665,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
if (LeadingZero) {
if (UniquedVals[Multiple-1].getNode() == 0)
return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
if (Val < 16)
return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
}
@ -694,7 +694,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
unsigned ValSizeInBytes = 0;
uint64_t Value = 0;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
Value = CN->getValue();
Value = CN->getZExtValue();
ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
@ -744,11 +744,11 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) {
if (N->getOpcode() != ISD::Constant)
return false;
Imm = (short)cast<ConstantSDNode>(N)->getValue();
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
if (N->getValueType(0) == MVT::i32)
return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
else
return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
}
static bool isIntS16Immediate(SDValue Op, short &Imm) {
return isIntS16Immediate(Op.getNode(), Imm);
@ -824,7 +824,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
return true; // [r+i]
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
// Match LOAD (ADD (X, Lo(G))).
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
&& "Cannot handle constant offsets yet!");
Disp = N.getOperand(1).getOperand(0); // The global address.
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
@ -867,8 +867,8 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
// Handle 32-bit sext immediates with LIS + addr mode.
if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getValue() == (int)CN->getValue()) {
int Addr = (int)CN->getValue();
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
@ -936,7 +936,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
return true; // [r+i]
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
// Match LOAD (ADD (X, Lo(G))).
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
&& "Cannot handle constant offsets yet!");
Disp = N.getOperand(1).getOperand(0); // The global address.
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
@ -966,7 +966,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
}
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
// Loading from a constant address. Verify low two bits are clear.
if ((CN->getValue() & 3) == 0) {
if ((CN->getZExtValue() & 3) == 0) {
// If this address fits entirely in a 14-bit sext immediate field, codegen
// this as "d, 0"
short Imm;
@ -978,8 +978,8 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
// Fold the low-part of 32-bit absolute addresses into addr mode.
if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getValue() == (int)CN->getValue()) {
int Addr = (int)CN->getValue();
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
int Addr = (int)CN->getZExtValue();
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
@ -1355,7 +1355,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
MachineRegisterInfo &RegInfo = MF.getRegInfo();
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@ -1881,12 +1881,13 @@ PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
SelectionDAG& DAG) const {
// Variable argument functions are not supported.
if (!PerformTailCallOpt ||
cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false;
cast<ConstantSDNode>(Call.getOperand(2))->getZExtValue() != 0)
return false;
if (CheckTailCallReturnConstraints(Call, Ret)) {
MachineFunction &MF = DAG.getMachineFunction();
unsigned CallerCC = MF.getFunction()->getCallingConv();
unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
unsigned CalleeCC= cast<ConstantSDNode>(Call.getOperand(1))->getZExtValue();
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
// Functions containing by val parameters are not supported.
for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) {
@ -1917,12 +1918,12 @@ static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
if (!C) return 0;
int Addr = C->getValue();
int Addr = C->getZExtValue();
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
(Addr << 6 >> 6) != Addr)
return 0; // Top 6 bits have to be sext of immediate.
return DAG.getConstant((int)C->getValue() >> 2,
return DAG.getConstant((int)C->getZExtValue() >> 2,
DAG.getTargetLoweringInfo().getPointerTy()).getNode();
}
@ -2070,10 +2071,10 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget,
TargetMachine &TM) {
SDValue Chain = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
CC == CallingConv::Fast && PerformTailCallOpt;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue() != 0
&& CC == CallingConv::Fast && PerformTailCallOpt;
SDValue Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
@ -3108,7 +3109,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
continue;
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize));
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
assert(CN->getValueType(0) == MVT::f32 &&
"Only one legal FP vector type!");
@ -3543,7 +3544,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
continue; // Undef, ignore it.
unsigned ByteSource =
cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
if ((ByteSource & 3) != j) {
isFourElementShuffle = false;
break;
@ -3600,7 +3601,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
SrcElt = 0;
else
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
for (unsigned j = 0; j != BytesPerElement; ++j)
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
@ -3617,7 +3618,8 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
/// information about the intrinsic.
static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
bool &isDot) {
unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
unsigned IntrinsicID =
cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
CompareOpc = -1;
isDot = false;
switch (IntrinsicID) {
@ -3694,7 +3696,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
// Unpack the result based on how the target uses it.
unsigned BitNo; // Bit # of CR6.
bool InvertBit; // Invert result?
switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
default: // Can't happen, don't crash on invalid number though.
case 0: // Return the value of the EQ bit of CR6.
BitNo = 0; InvertBit = false;
@ -4400,19 +4402,19 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
default: break;
case PPCISD::SHL:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
if (C->getValue() == 0) // 0 << V -> 0.
if (C->getZExtValue() == 0) // 0 << V -> 0.
return N->getOperand(0);
}
break;
case PPCISD::SRL:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
if (C->getValue() == 0) // 0 >>u V -> 0.
if (C->getZExtValue() == 0) // 0 >>u V -> 0.
return N->getOperand(0);
}
break;
case PPCISD::SRA:
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
if (C->getValue() == 0 || // 0 >>s V -> 0.
if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
C->isAllOnesValue()) // -1 >>s V -> -1.
return N->getOperand(0);
}
@ -4591,7 +4593,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// If this is a comparison against something other than 0/1, then we know
// that the condition is never/always true.
unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
if (Val != 0 && Val != 1) {
if (CC == ISD::SETEQ) // Cond never true, remove branch.
return N->getOperand(0);
@ -4615,7 +4617,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// Unpack the result based on how the target uses it.
PPC::Predicate CompOpc;
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
default: // Can't happen, don't crash on invalid number though.
case 0: // Branch on the value of the EQ bit of CR6.
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
@ -4663,7 +4665,7 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
break;
}
case ISD::INTRINSIC_WO_CHAIN: {
switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
default: break;
case Intrinsic::ppc_altivec_vcmpbfp_p:
case Intrinsic::ppc_altivec_vcmpeqfp_p:
@ -4750,7 +4752,7 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
case 'P': {
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
if (!CST) return; // Must be an immediate to match.
unsigned Value = CST->getValue();
unsigned Value = CST->getZExtValue();
switch (Letter) {
default: assert(0 && "Unknown constraint letter!");
case 'I': // "I" is a signed 16-bit constant.
@ -4846,7 +4848,7 @@ bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
MachineFunction &MF = DAG.getMachineFunction();
@ -4863,7 +4865,7 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();

8
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -34,22 +34,22 @@ def symbolLo64 : Operand<i64> {
def SHL64 : SDNodeXForm<imm, [{
// Transformation function: 63 - imm
return getI32Imm(63 - N->getValue());
return getI32Imm(63 - N->getZExtValue());
}]>;
def SRL64 : SDNodeXForm<imm, [{
// Transformation function: 64 - imm
return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
}]>;
def HI32_48 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getValue() >> 32));
return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
}]>;
def HI48_64 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getValue() >> 48));
return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
}]>;

28
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -155,47 +155,47 @@ def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
def SHL32 : SDNodeXForm<imm, [{
// Transformation function: 31 - imm
return getI32Imm(31 - N->getValue());
return getI32Imm(31 - N->getZExtValue());
}]>;
def SRL32 : SDNodeXForm<imm, [{
// Transformation function: 32 - imm
return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
}]>;
def LO16 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm((unsigned short)N->getValue());
return getI32Imm((unsigned short)N->getZExtValue());
}]>;
def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned)N->getValue() >> 16);
return getI32Imm((unsigned)N->getZExtValue() >> 16);
}]>;
def HA16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
signed int Val = N->getValue();
signed int Val = N->getZExtValue();
return getI32Imm((Val - (signed short)Val) >> 16);
}]>;
def MB : SDNodeXForm<imm, [{
// Transformation function: get the start bit of a mask
unsigned mb, me;
(void)isRunOfOnes((unsigned)N->getValue(), mb, me);
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
return getI32Imm(mb);
}]>;
def ME : SDNodeXForm<imm, [{
// Transformation function: get the end bit of a mask
unsigned mb, me;
(void)isRunOfOnes((unsigned)N->getValue(), mb, me);
(void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
return getI32Imm(me);
}]>;
def maskimm32 : PatLeaf<(imm), [{
// maskImm predicate - True if immediate is a run of ones.
unsigned mb, me;
if (N->getValueType(0) == MVT::i32)
return isRunOfOnes((unsigned)N->getValue(), mb, me);
return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
else
return false;
}]>;
@ -204,14 +204,14 @@ def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
if (N->getValueType(0) == MVT::i32)
return (int32_t)N->getValue() == (short)N->getValue();
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getValue() == (short)N->getValue();
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
}]>;
def immZExt16 : PatLeaf<(imm), [{
// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
// field. Used by instructions like 'ori'.
return (uint64_t)N->getValue() == (unsigned short)N->getValue();
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>;
// imm16Shifted* - These match immediates where the low 16-bits are zero. There
@ -222,18 +222,18 @@ def immZExt16 : PatLeaf<(imm), [{
def imm16ShiftedZExt : PatLeaf<(imm), [{
// imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
// immediate are set. Used by instructions like 'xoris'.
return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
}], HI16>;
def imm16ShiftedSExt : PatLeaf<(imm), [{
// imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
// immediate are set. Used by instructions like 'addis'. Identical to
// imm16ShiftedZExt in 32-bit mode.
if (N->getValue() & 0xFFFF) return false;
if (N->getZExtValue() & 0xFFFF) return false;
if (N->getValueType(0) == MVT::i32)
return true;
// For 64-bit, make sure it is sext right.
return N->getValue() == (uint64_t)(int)N->getValue();
return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
}], HI16>;

2
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -91,7 +91,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
} else {
Base = Addr.getOperand(0);
}
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}

13
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -224,10 +224,10 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
}
static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
SDValue Chain = Op.getOperand(0);
SDValue Callee = Op.getOperand(4);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
#if 0
// Analyze operands of the call, assigning locations to each operand.
@ -691,7 +691,8 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
ISD::CondCode CC, unsigned &SPCC) {
if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
if (isa<ConstantSDNode>(RHS) &&
cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
CC == ISD::SETNE &&
((LHS.getOpcode() == SPISD::SELECT_ICC &&
LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
@ -699,10 +700,10 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
isa<ConstantSDNode>(LHS.getOperand(0)) &&
isa<ConstantSDNode>(LHS.getOperand(1)) &&
cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
SDValue CMPCC = LHS.getOperand(3);
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
LHS = CMPCC.getOperand(0);
RHS = CMPCC.getOperand(1);
}

14
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -45,25 +45,29 @@ def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
def simm11 : PatLeaf<(imm), [{
// simm11 predicate - True if the imm fits in a 11-bit sign extended field.
return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
return (((int)N->getZExtValue() << (32-11)) >> (32-11)) ==
(int)N->getZExtValue();
}]>;
def simm13 : PatLeaf<(imm), [{
// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
return (((int)N->getZExtValue() << (32-13)) >> (32-13)) ==
(int)N->getZExtValue();
}]>;
def LO10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
MVT::i32);
}]>;
def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
}]>;
def SETHIimm : PatLeaf<(imm), [{
return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
return (((unsigned)N->getZExtValue() >> 10) << 10) ==
(unsigned)N->getZExtValue();
}], HI22>;
// Addressing modes.

20
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -866,7 +866,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
if (ConstantSDNode
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
unsigned Val = CN->getValue();
unsigned Val = CN->getZExtValue();
if (Val == 1 || Val == 2 || Val == 3) {
AM.Scale = 1 << Val;
SDValue ShVal = N.getNode()->getOperand(0);
@ -879,7 +879,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
AM.IndexReg = ShVal.getNode()->getOperand(0);
ConstantSDNode *AddVal =
cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
uint64_t Disp = AM.Disp + (AddVal->getValue() << Val);
uint64_t Disp = AM.Disp + (AddVal->getZExtValue() << Val);
if (isInt32(Disp))
AM.Disp = Disp;
else
@ -906,8 +906,9 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
!AM.isRIPRel) {
if (ConstantSDNode
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
AM.Scale = unsigned(CN->getValue())-1;
if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
CN->getZExtValue() == 9) {
AM.Scale = unsigned(CN->getZExtValue())-1;
SDValue MulVal = N.getNode()->getOperand(0);
SDValue Reg;
@ -920,7 +921,8 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
Reg = MulVal.getNode()->getOperand(0);
ConstantSDNode *AddVal =
cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
uint64_t Disp = AM.Disp + AddVal->getZExtValue() *
CN->getZExtValue();
if (isInt32(Disp))
AM.Disp = Disp;
else
@ -963,7 +965,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
isInt32(AM.Disp + CN->getSignExtended()) &&
// Check to see if the LHS & C is zero.
CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
AM.Disp += CN->getValue();
AM.Disp += CN->getZExtValue();
return false;
}
AM = Backup;
@ -994,7 +996,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
break;
// Verify that the shift amount is something we can fold.
unsigned ShiftCst = C1->getValue();
unsigned ShiftCst = C1->getZExtValue();
if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
break;
@ -1065,7 +1067,7 @@ bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
/// constant +0.0.
static inline bool isZeroNode(SDValue Elt) {
return ((isa<ConstantSDNode>(Elt) &&
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
(isa<ConstantFPSDNode>(Elt) &&
cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
}
@ -1288,7 +1290,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
if (N.getNode()->getValueType(0) == PtrVT &&
N0.getOpcode() == X86ISD::Wrapper &&
N1.getOpcode() == ISD::Constant) {
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getZExtValue();
SDValue C(0, 0);
// TODO: handle ExternalSymbolSDNode.
if (GlobalAddressSDNode *G =

144
lib/Target/X86/X86ISelLowering.cpp
View File

@ -982,7 +982,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
bool isVarArg =
cast<ConstantSDNode>(TheCall->getOperand(2))->getZExtValue() != 0;
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
@ -1069,11 +1070,11 @@ static bool ArgsAreStructReturn(SDValue Op) {
/// the callee to pop its own arguments. Callee pop is necessary to support tail
/// calls.
bool X86TargetLowering::IsCalleePop(SDValue Op) {
bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
if (IsVarArg)
return false;
switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
default:
return false;
case CallingConv::X86_StdCall:
@ -1088,7 +1089,7 @@ bool X86TargetLowering::IsCalleePop(SDValue Op) {
/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
/// FORMAL_ARGUMENTS node.
CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Subtarget->is64Bit()) {
if (Subtarget->isTargetWin64())
@ -1113,7 +1114,7 @@ CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
NameDecorationStyle
X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (CC == CallingConv::X86_FastCall)
return FastCall;
else if (CC == CallingConv::X86_StdCall)
@ -1191,7 +1192,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
MachineFrameInfo *MFI = MF.getFrameInfo();
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = MF.getFunction()->getCallingConv();
bool Is64Bit = Subtarget->is64Bit();
bool IsWin64 = Subtarget->isTargetWin64();
@ -1470,9 +1471,9 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
SDValue Chain = Op.getOperand(0);
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue() != 0
&& CC == CallingConv::Fast && PerformTailCallOpt;
SDValue Callee = Op.getOperand(4);
bool Is64Bit = Subtarget->is64Bit();
@ -1863,7 +1864,7 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
if (CheckTailCallReturnConstraints(Call, Ret)) {
MachineFunction &MF = DAG.getMachineFunction();
unsigned CallerCC = MF.getFunction()->getCallingConv();
unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
unsigned CalleeCC= cast<ConstantSDNode>(Call.getOperand(1))->getZExtValue();
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
SDValue Callee = Call.getOperand(4);
// On x86/32Bit PIC/GOT tail calls are supported.
@ -1933,7 +1934,7 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
// X < 0 -> X == 0, jump on sign.
X86CC = X86::COND_S;
return true;
} else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
} else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
// X < 1 -> X <= 0
RHS = DAG.getConstant(0, RHS.getValueType());
X86CC = X86::COND_LE;
@ -2050,7 +2051,7 @@ static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
if (Op.getOpcode() == ISD::UNDEF)
return true;
unsigned Val = cast<ConstantSDNode>(Op)->getValue();
unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
return (Val >= Low && Val < Hi);
}
@ -2059,7 +2060,7 @@ static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
static bool isUndefOrEqual(SDValue Op, unsigned Val) {
if (Op.getOpcode() == ISD::UNDEF)
return true;
return cast<ConstantSDNode>(Op)->getValue() == Val;
return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
}
/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
@ -2075,7 +2076,7 @@ bool X86::isPSHUFDMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
if (cast<ConstantSDNode>(Arg)->getValue() >= e)
if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
return false;
}
@ -2095,7 +2096,7 @@ bool X86::isPSHUFHWMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
if (cast<ConstantSDNode>(Arg)->getValue() != i)
if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
return false;
}
@ -2104,7 +2105,7 @@ bool X86::isPSHUFHWMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val < 4 || Val > 7)
return false;
}
@ -2420,7 +2421,7 @@ bool X86::isMOVSHDUPMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val != 1) return false;
}
@ -2429,7 +2430,7 @@ bool X86::isMOVSHDUPMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val != 3) return false;
HasHi = true;
}
@ -2451,7 +2452,7 @@ bool X86::isMOVSLDUPMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val != 0) return false;
}
@ -2460,7 +2461,7 @@ bool X86::isMOVSLDUPMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val != 2) return false;
HasHi = true;
}
@ -2508,7 +2509,7 @@ static bool isSplatMask(SDNode *N) {
}
// Make sure it is a splat of the first vector operand.
return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
}
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
@ -2544,7 +2545,7 @@ unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
unsigned Val = 0;
SDValue Arg = N->getOperand(NumOperands-i-1);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val >= NumOperands) Val -= NumOperands;
Mask |= Val;
if (i != NumOperands - 1)
@ -2564,7 +2565,7 @@ unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
unsigned Val = 0;
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Mask |= (Val - 4);
if (i != 4)
Mask <<= 2;
@ -2583,7 +2584,7 @@ unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
unsigned Val = 0;
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF)
Val = cast<ConstantSDNode>(Arg)->getValue();
Val = cast<ConstantSDNode>(Arg)->getZExtValue();
Mask |= Val;
if (i != 0)
Mask <<= 2;
@ -2606,7 +2607,7 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val >= 4)
return false;
}
@ -2616,7 +2617,7 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
SDValue Arg = N->getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) continue;
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val < 4 || Val > 7)
return false;
}
@ -2642,7 +2643,7 @@ static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
continue;
}
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val < NumElems)
MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
else
@ -2669,7 +2670,7 @@ SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
continue;
}
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val < NumElems)
MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
else
@ -2762,7 +2763,7 @@ static bool isUndefShuffle(SDNode *N) {
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF) {
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
return false;
else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
@ -2776,7 +2777,7 @@ static bool isUndefShuffle(SDNode *N) {
/// constant +0.0.
static inline bool isZeroNode(SDValue Elt) {
return ((isa<ConstantSDNode>(Elt) &&
cast<ConstantSDNode>(Elt)->getValue() == 0) ||
cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
(isa<ConstantFPSDNode>(Elt) &&
cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
}
@ -2796,7 +2797,7 @@ static bool isZeroShuffle(SDNode *N) {
if (Arg.getOpcode() == ISD::UNDEF)
continue;
unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Idx < NumElems) {
unsigned Opc = V1.getNode()->getOpcode();
if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
@ -2865,7 +2866,7 @@ static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() != ISD::UNDEF) {
unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Val > NumElems) {
Arg = DAG.getConstant(NumElems, Arg.getValueType());
Changed = true;
@ -3029,7 +3030,7 @@ static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
if (Idx.getOpcode() == ISD::UNDEF)
continue;
unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
if (Index < NumElems)
SeenV1 = true;
else {
@ -3394,7 +3395,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
int QuadIdx = EltIdx / 4;
++LowQuad[QuadIdx];
}
@ -3414,7 +3415,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
int QuadIdx = EltIdx / 4;
++HighQuad[QuadIdx];
}
@ -3462,7 +3463,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
MaskVec.push_back(Elt);
InOrder.set(i);
} else {
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx != i)
AnyOutOrder = true;
@ -3496,7 +3497,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
MaskVec.push_back(Elt);
InOrder.set(i);
} else {
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx != i)
AnyOutOrder = true;
@ -3522,7 +3523,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue Elt = MaskElts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
SDValue ExtOp = (EltIdx < 8)
? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT))
@ -3553,7 +3554,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
++V2InOrder;
continue;
}
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx == i) {
V1Elts.push_back(Elt);
V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
@ -3590,7 +3591,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
continue;
}
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx >= 8)
MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
else
@ -3605,7 +3606,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx < 8)
continue;
SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
@ -3621,7 +3622,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT));
NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
@ -3668,7 +3669,7 @@ SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
SDValue Elt = PermMask.getOperand(i+j);
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (StartIdx == ~0U)
StartIdx = EltIdx - (EltIdx % Scale);
if (EltIdx != StartIdx + j)
@ -3737,7 +3738,7 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
if (Elt.getOpcode() == ISD::UNDEF) {
Locs[i] = std::make_pair(-1, -1);
} else {
unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
if (Val < 4) {
Locs[i] = std::make_pair(0, NumLo);
@ -3795,7 +3796,7 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
SDValue Elt = PermMask.getOperand(HiIndex);
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
if (Val >= 4)
break;
}
@ -3820,11 +3821,13 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
Mask1[2] = PermMask.getOperand(2);
Mask1[3] = PermMask.getOperand(3);
if (Mask1[2].getOpcode() != ISD::UNDEF)
Mask1[2] = DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getValue()+4,
MaskEVT);
Mask1[2] =
DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
MaskEVT);
if (Mask1[3].getOpcode() != ISD::UNDEF)
Mask1[3] = DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getValue()+4,
MaskEVT);
Mask1[3] =
DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
MaskEVT);
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
}
@ -3848,7 +3851,7 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
SDValue Elt = PermMask.getOperand(i);
if (Elt.getOpcode() == ISD::UNDEF) {
Locs[i] = std::make_pair(-1, -1);
} else if (cast<ConstantSDNode>(Elt)->getValue() < 4) {
} else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
Locs[i] = std::make_pair(MaskIdx, LoIdx);
(*MaskPtr)[LoIdx] = Elt;
LoIdx++;
@ -4144,7 +4147,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
// TODO: handle v16i8.
if (VT.getSizeInBits() == 16) {
SDValue Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
return DAG.getNode(ISD::TRUNCATE, MVT::i16,
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
@ -4158,7 +4161,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
} else if (VT.getSizeInBits() == 32) {
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
return Op;
// SHUFPS the element to the lowest double word, then movss.
@ -4183,7 +4186,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
// FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
// FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
// to match extract_elt for f64.
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
return Op;
@ -4225,7 +4228,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
if (N1.getValueType() != MVT::i32)
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(Opc, VT, N0, N1, N2);
} else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
// Bits [7:6] of the constant are the source select. This will always be
@ -4236,7 +4239,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
// value of the incoming immediate.
// Bits [3:0] of the constant are the zero mask. The DAG Combiner may
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
}
return SDValue();
@ -4263,7 +4266,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
if (N1.getValueType() != MVT::i32)
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
}
return SDValue();
@ -5089,7 +5092,8 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
/// address value and run time information about the CPU.
if ((Align & 3) != 0 ||
!ConstantSize ||
ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
ConstantSize->getZExtValue() >
getSubtarget()->getMaxInlineSizeThreshold()) {
SDValue InFlag(0, 0);
// Check to see if there is a specialized entry-point for memory zeroing.
@ -5116,7 +5120,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
return SDValue();
}
uint64_t SizeVal = ConstantSize->getValue();
uint64_t SizeVal = ConstantSize->getZExtValue();
SDValue InFlag(0, 0);
MVT AVT;
SDValue Count;
@ -5125,7 +5129,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
bool TwoRepStos = false;
if (ValC) {
unsigned ValReg;
uint64_t Val = ValC->getValue() & 255;
uint64_t Val = ValC->getZExtValue() & 255;
// If the value is a constant, then we can potentially use larger sets.
switch (Align & 3) {
@ -5227,7 +5231,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
if (!ConstantSize)
return SDValue();
uint64_t SizeVal = ConstantSize->getValue();
uint64_t SizeVal = ConstantSize->getZExtValue();
if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
return SDValue();
@ -5387,7 +5391,7 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
SDValue
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
// Comparison intrinsics.
@ -5585,7 +5589,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
// Just load the return address
@ -5595,7 +5599,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
@ -7087,16 +7091,16 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
default: break;
case 'I':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
if (C->getValue() <= 31) {
Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
if (C->getZExtValue() <= 31) {
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
break;
}
}
return;
case 'N':
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
if (C->getValue() <= 255) {
Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
if (C->getZExtValue() <= 255) {
Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
break;
}
}
@ -7104,7 +7108,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
case 'i': {
// Literal immediates are always ok.
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
break;
}
@ -7120,12 +7124,12 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
if (C && GA) {
Offset = GA->getOffset()+C->getValue();
Offset = GA->getOffset()+C->getZExtValue();
} else {
C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
if (C && GA)
Offset = GA->getOffset()+C->getValue();
Offset = GA->getOffset()+C->getZExtValue();
else
C = 0, GA = 0;
}

8
lib/Target/X86/X86Instr64bit.td
View File

@ -46,25 +46,25 @@ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
def i64immSExt32 : PatLeaf<(i64 imm), [{
// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
// sign extended field.
return (int64_t)N->getValue() == (int32_t)N->getValue();
return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
}]>;
def i64immZExt32 : PatLeaf<(i64 imm), [{
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
// unsignedsign extended field.
return (uint64_t)N->getValue() == (uint32_t)N->getValue();
return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
}]>;
def i64immSExt8 : PatLeaf<(i64 imm), [{
// i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
// sign extended field.
return (int64_t)N->getValue() == (int8_t)N->getValue();
return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>;
def i64immFFFFFFFF : PatLeaf<(i64 imm), [{
// i64immFFFFFFFF - True if this is a specific constant we can't write in
// tblgen files.
return N->getValue() == 0x00000000FFFFFFFFULL;
return N->getZExtValue() == 0x00000000FFFFFFFFULL;
}]>;

4
lib/Target/X86/X86InstrInfo.td
View File

@ -219,13 +219,13 @@ def X86_COND_S : PatLeaf<(i8 15)>;
def i16immSExt8 : PatLeaf<(i16 imm), [{
// i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
// sign extended field.
return (int16_t)N->getValue() == (int8_t)N->getValue();
return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>;
def i32immSExt8 : PatLeaf<(i32 imm), [{
// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
// sign extended field.
return (int32_t)N->getValue() == (int8_t)N->getValue();
return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>;
// Helper fragments for loads.

2
lib/Target/X86/X86InstrSSE.td
View File

@ -168,7 +168,7 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{
def PSxLDQ_imm : SDNodeXForm<imm, [{
// Transformation function: imm >> 3
return getI32Imm(N->getValue() >> 3);
return getI32Imm(N->getZExtValue() >> 3);
}]>;
// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,

11
utils/TableGen/DAGISelEmitter.cpp
View File

@ -781,7 +781,7 @@ public:
}
emitCode("SDValue " + TmpVar +
" = CurDAG->getTargetConstant(((" + CastType +
") cast<ConstantSDNode>(" + Val + ")->getValue()), " +
") cast<ConstantSDNode>(" + Val + ")->getZExtValue()), " +
getEnumName(N->getTypeNum(0)) + ");");
// Add Tmp<ResNo> to VariableMap, so that we don't multiply select this
// value if used multiple times by this pattern result.
@ -1839,7 +1839,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
OS << " N.getNode()->dump(CurDAG);\n";
} else {
OS << " unsigned iid = cast<ConstantSDNode>(N.getOperand("
"N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"
"N.getOperand(0).getValueType() == MVT::Other))->getZExtValue();\n"
<< " cerr << \"intrinsic %\"<< "
"Intrinsic::getName((Intrinsic::ID)iid);\n";
}
@ -1914,7 +1914,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n"
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getZExtValue();\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EXTRACT_SUBREG,\n"
@ -1925,7 +1925,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " SDValue N2 = N.getOperand(2);\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getValue();\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getZExtValue();\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N1);\n"
<< " AddToISelQueue(N0);\n"
@ -2036,7 +2036,8 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " N.getNode()->dump(CurDAG);\n"
<< " } else {\n"
<< " unsigned iid = cast<ConstantSDNode>(N.getOperand("
"N.getOperand(0).getValueType() == MVT::Other))->getValue();\n"
"N.getOperand(0).getValueType() == "
"MVT::Other))->getZExtValue();\n"
<< " cerr << \"intrinsic %\"<< "
"Intrinsic::getName((Intrinsic::ID)iid);\n"
<< " }\n"