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Adjust to change in ctor
llvm-svn: 23585
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@ -43,7 +43,7 @@ namespace {
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SparcV9::g7, SparcV9::o6
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};
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struct IRClass : public TargetRegisterClass {
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IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {}
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IRClass() : TargetRegisterClass(MVT::i64, 8, 8, IR, IR + 32) {}
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} IRInstance;
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@ -71,7 +71,7 @@ namespace {
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// one (32, 34, ...), and they must contain double-fp or quad-fp
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// values... see below about the aliasing problems.
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struct FRClass : public TargetRegisterClass {
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FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {}
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FRClass() : TargetRegisterClass(MVT::f32, 4, 8, FR, FR + 64) {}
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} FRInstance;
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@ -80,7 +80,7 @@ namespace {
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SparcV9::xcc, SparcV9::icc, SparcV9::ccr
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};
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struct ICCRClass : public TargetRegisterClass {
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ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {}
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ICCRClass() : TargetRegisterClass(MVT::i1, 1, 8, ICCR, ICCR + 3) {}
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} ICCRInstance;
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@ -89,7 +89,7 @@ namespace {
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SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
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};
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struct FCCRClass : public TargetRegisterClass {
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FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {}
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FCCRClass() : TargetRegisterClass(MVT::i1, 1, 8, FCCR, FCCR + 4) {}
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} FCCRInstance;
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@ -98,7 +98,7 @@ namespace {
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SparcV9::fsr
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};
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struct SRClass : public TargetRegisterClass {
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SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {}
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SRClass() : TargetRegisterClass(MVT::i64, 8, 8, SR, SR + 1) {}
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} SRInstance;
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