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Clean up some code for clarity.

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llvm-svn: 128953
This commit is contained in:
Bob Wilson 2011-04-05 23:03:25 +00:00
parent 715cc35206
commit 89dce9ab06
1 changed files with 24 additions and 5 deletions
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29
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -454,6 +454,25 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
unsigned PRegNum = PMO.isUndef() ? UINT_MAX unsigned PRegNum = PMO.isUndef() ? UINT_MAX
: getARMRegisterNumbering(PReg); : getARMRegisterNumbering(PReg);
unsigned Count = 1; unsigned Count = 1;
unsigned Limit = ~0U;
// vldm / vstm limit are 32 for S variants, 16 for D variants.
switch (Opcode) {
default: break;
case ARM::VSTRS:
Limit = 32;
break;
case ARM::VSTRD:
Limit = 16;
break;
case ARM::VLDRD:
Limit = 16;
break;
case ARM::VLDRS:
Limit = 32;
break;
}
for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) { for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
int NewOffset = MemOps[i].Offset; int NewOffset = MemOps[i].Offset;
@ -461,13 +480,13 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
unsigned RegNum = MO.isUndef() ? UINT_MAX unsigned RegNum = MO.isUndef() ? UINT_MAX
: getARMRegisterNumbering(Reg); : getARMRegisterNumbering(Reg);
// Register numbers must be in ascending order. For VFP, the registers // Register numbers must be in ascending order. For VFP / NEON load and
// must also be consecutive and there is a limit of 16 double-word // store multiples, the registers must also be consecutive and within the
// registers per instruction. // limit on the number of registers per instruction.
if (Reg != ARM::SP && if (Reg != ARM::SP &&
NewOffset == Offset + (int)Size && NewOffset == Offset + (int)Size &&
((isNotVFP && RegNum > PRegNum) ((isNotVFP && RegNum > PRegNum) ||
|| ((Size < 8 || Count < 16) && RegNum == PRegNum+1))) { ((Count < Limit) && RegNum == PRegNum+1))) {
Offset += Size; Offset += Size;
PRegNum = RegNum; PRegNum = RegNum;
++Count; ++Count;