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[AMDGPU, docs] Fix typos
Reviewed By: t-tye, Flakebi Differential Revision: https://reviews.llvm.org/D86340
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@ -106,7 +106,7 @@ programming languages used in ML and HPC. The extensions also include improved
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support for optimized code on any architecture. Some of the generalizations may
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also benefit other issues that have been raised.
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The extensions have evolved though collaboration with many individuals and
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The extensions have evolved through collaboration with many individuals and
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active prototyping within the GDB debugger and LLVM compiler. Input has also
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been very much appreciated from the developers working on the Perforce TotalView
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HPC Debugger and GCC compiler.
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@ -147,7 +147,7 @@ be generated to describe the CFI as only a single expression is required for
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the whole vector register, rather than a separate expression for each lane's
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dword of the vector register. It also allows the compiler to produce DWARF
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that indexes the vector register if it spills scalar registers into portions
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of a vector registers.
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of a vector register.
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Since DWARF stack value entries have a base type and AMDGPU registers are a
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vector of dwords, the ability to specify that a base type is a vector is
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