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Change the 'isStore' inferrer to look for 'SDNPMayStore'

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instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
This commit is contained in:
Chris Lattner 2008-01-06 06:44:58 +00:00
parent 2bb919b542
commit 8b4b75c771
10 changed files with 212 additions and 192 deletions
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3
lib/Target/Alpha/AlphaInstrFormats.td
View File

@ -38,10 +38,9 @@ class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
//3.3.1 //3.3.1
class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
: InstAlpha<opcode, asmstr, itin> { : InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern; let Pattern = pattern;
let isStore = store;
let isLoad = load; let isLoad = load;
let Defs = [R28]; //We may use this for frame index calculations, so reserve it here let Defs = [R28]; //We may use this for frame index calculations, so reserve it here

62
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -412,78 +412,78 @@ def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP),
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)", def LDQ : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow", def LDQr : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)", def LDL : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
[(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; [(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow", def LDLr : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; [(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)", def LDBU : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; [(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow", def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; [(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)", def LDWU : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
[(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>; [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow", def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>; [(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
} }
let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)", def STB : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow", def STBr : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>; [(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)", def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
[(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; [(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow", def STWr : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>; [(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)", def STL : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
[(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; [(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow", def STLr : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
[(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>; [(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)", def STQ : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
[(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>; [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow", def STQr : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
[(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>; [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
} }
//Load address //Load address
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)", def LDA : MForm<0x08, 0, "lda $RA,$DISP($RB)",
[(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>; [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow", def LDAr : MForm<0x08, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address
def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)", def LDAH : MForm<0x09, 0, "ldah $RA,$DISP($RB)",
[], s_lda>; //Load address high [], s_lda>; //Load address high
def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh", def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
[(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high
} }
let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)", def STS : MForm<0x26, 0, "sts $RA,$DISP($RB)",
[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>; [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow", def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>; [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
} }
let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)", def LDS : MForm<0x22, 1, "lds $RA,$DISP($RB)",
[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>; [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow", def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>; [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
} }
let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)", def STT : MForm<0x27, 0, "stt $RA,$DISP($RB)",
[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>; [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow", def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>; [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
} }
let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)", def LDT : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>; [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow", def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>; [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
} }
@ -557,13 +557,13 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
//load address, rellocated gpdist form //load address, rellocated gpdist form
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in { let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
} }
//Load quad, rellocated literal form //Load quad, rellocated literal form
let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in
def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal", def LDQl : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!literal",
[(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>; [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB), def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
(LDQl texternalsym:$ext, GPRC:$RB)>; (LDQl texternalsym:$ext, GPRC:$RB)>;

268
lib/Target/CellSPU/SPUInstrInfo.td
View File

@ -257,179 +257,177 @@ let isLoad = 1 in {
// Stores: // Stores:
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isStore = 1 in { def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), "stqd\t$rT, $src", LoadStore,
"stqd\t$rT, $src", LoadStore, [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
[(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store (v8i16 VECREG:$rT), dform_addr:$src)]>; [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store (v4i32 VECREG:$rT), dform_addr:$src)]>; [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store (v2i64 VECREG:$rT), dform_addr:$src)]>; [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store (v4f32 VECREG:$rT), dform_addr:$src)]>; [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src), def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store (v2f64 VECREG:$rT), dform_addr:$src)]>; [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src), def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store GPRC:$rT, dform_addr:$src)]>; [(store GPRC:$rT, dform_addr:$src)]>;
def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src), def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R64C:$rT, dform_addr:$src)]>; [(store R64C:$rT, dform_addr:$src)]>;
def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src), def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R32C:$rT, dform_addr:$src)]>; [(store R32C:$rT, dform_addr:$src)]>;
// Floating Point // Floating Point
def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src), def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R32FP:$rT, dform_addr:$src)]>; [(store R32FP:$rT, dform_addr:$src)]>;
def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src), def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R64FP:$rT, dform_addr:$src)]>; [(store R64FP:$rT, dform_addr:$src)]>;
def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src), def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R16C:$rT, dform_addr:$src)]>; [(store R16C:$rT, dform_addr:$src)]>;
def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src), def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
"stqd\t$rT, $src", LoadStore, "stqd\t$rT, $src", LoadStore,
[(store R8C:$rT, dform_addr:$src)]>; [(store R8C:$rT, dform_addr:$src)]>;
def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v16i8 VECREG:$rT), aform_addr:$src)]>; [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v8i16 VECREG:$rT), aform_addr:$src)]>; [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v4i32 VECREG:$rT), aform_addr:$src)]>; [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v2i64 VECREG:$rT), aform_addr:$src)]>; [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v4f32 VECREG:$rT), aform_addr:$src)]>; [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src), def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v2f64 VECREG:$rT), aform_addr:$src)]>; [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src), def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store GPRC:$rT, aform_addr:$src)]>; [(store GPRC:$rT, aform_addr:$src)]>;
def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src), def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store R64C:$rT, aform_addr:$src)]>; [(store R64C:$rT, aform_addr:$src)]>;
def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src), def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store R32C:$rT, aform_addr:$src)]>; [(store R32C:$rT, aform_addr:$src)]>;
// Floating Point // Floating Point
def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src), def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store R32FP:$rT, aform_addr:$src)]>; [(store R32FP:$rT, aform_addr:$src)]>;
def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src), def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store R64FP:$rT, aform_addr:$src)]>; [(store R64FP:$rT, aform_addr:$src)]>;
def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src), def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store R16C:$rT, aform_addr:$src)]>; [(store R16C:$rT, aform_addr:$src)]>;
def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
"stqa\t$rT, $src", LoadStore,
[(store R8C:$rT, aform_addr:$src)]>;
def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
"stqx\t$rT, $src", LoadStore, "stqa\t$rT, $src", LoadStore,
[(store (v16i8 VECREG:$rT), xform_addr:$src)]>; [(store R8C:$rT, aform_addr:$src)]>;
def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store (v8i16 VECREG:$rT), xform_addr:$src)]>; [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store (v4i32 VECREG:$rT), xform_addr:$src)]>; [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store (v2i64 VECREG:$rT), xform_addr:$src)]>; [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store (v4f32 VECREG:$rT), xform_addr:$src)]>; [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src), def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store (v2f64 VECREG:$rT), xform_addr:$src)]>; [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src), def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store GPRC:$rT, xform_addr:$src)]>; [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
def STQXr64: def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src), "stqx\t$rT, $src", LoadStore,
"stqx\t$rT, $src", LoadStore, [(store GPRC:$rT, xform_addr:$src)]>;
[(store R64C:$rT, xform_addr:$src)]>;
def STQXr32: def STQXr64:
RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src), RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store R32C:$rT, xform_addr:$src)]>; [(store R64C:$rT, xform_addr:$src)]>;
// Floating Point def STQXr32:
def STQXf32: RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src), "stqx\t$rT, $src", LoadStore,
"stqx\t$rT, $src", LoadStore, [(store R32C:$rT, xform_addr:$src)]>;
[(store R32FP:$rT, xform_addr:$src)]>;
def STQXf64: // Floating Point
RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src), def STQXf32:
"stqx\t$rT, $src", LoadStore, RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
[(store R64FP:$rT, xform_addr:$src)]>; "stqx\t$rT, $src", LoadStore,
[(store R32FP:$rT, xform_addr:$src)]>;
def STQXr16: def STQXf64:
RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src), RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store R16C:$rT, xform_addr:$src)]>; [(store R64FP:$rT, xform_addr:$src)]>;
def STQXr8: def STQXr16:
RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src), RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore, "stqx\t$rT, $src", LoadStore,
[(store R8C:$rT, xform_addr:$src)]>; [(store R16C:$rT, xform_addr:$src)]>;
def STQXr8:
RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
"stqx\t$rT, $src", LoadStore,
[(store R8C:$rT, xform_addr:$src)]>;
/* Store quadword, PC relative: Not much use at this point in time. Might /* Store quadword, PC relative: Not much use at this point in time. Might
be useful for relocatable code. be useful for relocatable code.
def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp), def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
"stqr\t$rT, $disp", LoadStore, "stqr\t$rT, $disp", LoadStore,
[(store VECREG:$rT, iaddr:$disp)]>; [(store VECREG:$rT, iaddr:$disp)]>;
*/ */
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Generate Controls for Insertion: // Generate Controls for Insertion:

1
lib/Target/Mips/MipsInstrInfo.td
View File

@ -213,7 +213,6 @@ class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>; [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
let isStore = 1 in
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>: class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
FI< op, FI< op,
(outs), (outs),

6
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -513,14 +513,10 @@ def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
isPPC64; isPPC64;
} let isStore = 1 in
let isStore = 1, PPC970_Unit = 2 in {
def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
"stdux $rS, $dst", LdStSTD, "stdux $rS, $dst", LdStSTD,
[]>, isPPC64; []>, isPPC64;
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),

12
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -52,7 +52,8 @@ def SDT_PPCstbrx : SDTypeProfile<0, 4, [
def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
[SDNPHasChain, SDNPMayStore]>;
// This sequence is used for long double->int conversions. It changes the // This sequence is used for long double->int conversions. It changes the
// bits in the FPSCR which is not modelled. // bits in the FPSCR which is not modelled.
@ -88,7 +89,8 @@ def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
[SDNPHasChain, SDNPMayStore]>;
// These are target-independent nodes, but have target-specific formats. // These are target-independent nodes, but have target-specific formats.
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
@ -119,7 +121,8 @@ def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>; def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>; def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
[SDNPHasChain, SDNPMayStore]>;
// Instructions to support dynamic alloca. // Instructions to support dynamic alloca.
def SDTDynOp : SDTypeProfile<1, 2, []>; def SDTDynOp : SDTypeProfile<1, 2, []>;
@ -639,6 +642,7 @@ let isStore = 1 in {
def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwux $rS, $rA, $rB", LdStGeneral, "stwux $rS, $rA, $rB", LdStGeneral,
[]>; []>;
}
def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
"sthbrx $rS, $dst", LdStGeneral, "sthbrx $rS, $dst", LdStGeneral,
[(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>, [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
@ -651,7 +655,7 @@ def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
"stfiwx $frS, $dst", LdStUX, "stfiwx $frS, $dst", LdStUX,
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
}
def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
"stfsx $frS, $dst", LdStUX, "stfsx $frS, $dst", LdStUX,
[(store F4RC:$frS, xaddr:$dst)]>; [(store F4RC:$frS, xaddr:$dst)]>;

7
lib/Target/TargetSelectionDAG.td
View File

@ -189,6 +189,7 @@ def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
def SDNPOutFlag : SDNodeProperty; // Write a flag result def SDNPOutFlag : SDNodeProperty; // Write a flag result
def SDNPInFlag : SDNodeProperty; // Read a flag operand def SDNPInFlag : SDNodeProperty; // Read a flag operand
def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Selection DAG Node definitions. // Selection DAG Node definitions.
@ -313,8 +314,10 @@ def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
// Do not use ld, st directly. Use load, extload, sextload, zextload, store, // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
// and truncst (see below). // and truncst (see below).
def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; def st : SDNode<"ISD::STORE" , SDTStore,
def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>; [SDNPHasChain, SDNPMayStore]>;
def ist : SDNode<"ISD::STORE" , SDTIStore,
[SDNPHasChain, SDNPMayStore]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;

2
utils/TableGen/CodeGenDAGPatterns.cpp
View File

@ -317,6 +317,8 @@ SDNodeInfo::SDNodeInfo(Record *R) : Def(R) {
Properties |= 1 << SDNPInFlag; Properties |= 1 << SDNPInFlag;
} else if (PropList[i]->getName() == "SDNPOptInFlag") { } else if (PropList[i]->getName() == "SDNPOptInFlag") {
Properties |= 1 << SDNPOptInFlag; Properties |= 1 << SDNPOptInFlag;
} else if (PropList[i]->getName() == "SDNPMayStore") {
Properties |= 1 << SDNPMayStore;
} else { } else {
cerr << "Unknown SD Node property '" << PropList[i]->getName() cerr << "Unknown SD Node property '" << PropList[i]->getName()
<< "' on node '" << R->getName() << "'!\n"; << "' on node '" << R->getName() << "'!\n";

11
utils/TableGen/CodeGenTarget.h
View File

@ -30,8 +30,15 @@ struct CodeGenRegister;
class CodeGenTarget; class CodeGenTarget;
// SelectionDAG node properties. // SelectionDAG node properties.
enum SDNP { SDNPCommutative, SDNPAssociative, SDNPHasChain, enum SDNP {
SDNPOutFlag, SDNPInFlag, SDNPOptInFlag }; SDNPCommutative,
SDNPAssociative,
SDNPHasChain,
SDNPOutFlag,
SDNPInFlag,
SDNPOptInFlag,
SDNPMayStore
};
/// getValueType - Return the MVT::ValueType that the specified TableGen record /// getValueType - Return the MVT::ValueType that the specified TableGen record
/// corresponds to. /// corresponds to.

32
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -157,9 +157,7 @@ public:
if (Pattern == 0) return; // No pattern. if (Pattern == 0) return; // No pattern.
// Assume there is no side-effect unless we see one. // Assume there is no side-effect unless we see one.
// FIXME: Enable this. NeverHasSideEffects = true;
//NeverHasSideEffects = true;
// FIXME: Assume only the first tree is the pattern. The others are clobber // FIXME: Assume only the first tree is the pattern. The others are clobber
// nodes. // nodes.
@ -176,10 +174,9 @@ private:
// Get information about the SDNode for the operator. // Get information about the SDNode for the operator.
const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
// If this is a store node, it obviously stores to memory. // If node writes to memory, it obviously stores to memory.
if (OpInfo.getEnumName() == "ISD::STORE") { if (OpInfo.hasProperty(SDNPMayStore)) {
isStore = true; isStore = true;
} else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
// If this is an intrinsic, analyze it. // If this is an intrinsic, analyze it.
if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
@ -196,15 +193,30 @@ private:
void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
bool &isStore, bool &isLoad, bool &isStore, bool &isLoad,
bool &NeverHasSideEffects) { bool &NeverHasSideEffects) {
isStore = Inst.isStore; isStore = isLoad = NeverHasSideEffects = false;
isLoad = Inst.isLoad;
NeverHasSideEffects = Inst.neverHasSideEffects;
InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef); InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
// InstAnalyzer only correctly analyzes isStore so far.
if (Inst.isStore) { // If the .td file explicitly sets isStore, use it.
// If we decided that this is a store from the pattern, then the .td file
// entry is redundant.
if (isStore)
fprintf(stderr, "Warning: isStore flag explicitly set on instruction '%s'"
" but flag already inferred from pattern.\n",
Inst.getName().c_str());
isStore = true;
}
// These two override everything.
isLoad = Inst.isLoad;
NeverHasSideEffects = Inst.neverHasSideEffects;
#if 0
// If the .td file explicitly says there is no side effect, believe it. // If the .td file explicitly says there is no side effect, believe it.
if (Inst.neverHasSideEffects) if (Inst.neverHasSideEffects)
NeverHasSideEffects = true; NeverHasSideEffects = true;
#endif
} }