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[PowerPC] Fix reversed bit issue in DCMX mask for "xvtstdcdp" and "xvtstdcsp" P9 implementation

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Did experiments on power 9 machine, checked the outputs for NaN & Infinity+
cases with corresponding DCMX bit set. Confirmed the DCMX mask bit for NaN and
infinity+ are reversed.

This patch fixes the issue.

Patch by Victor Huang.

Differential Revision: https://reviews.llvm.org/D59384

llvm-svn: 357494
This commit is contained in:
Stefan Pintilie 2019-04-02 16:56:01 +00:00
parent 07eb26281f
commit 8ceb0266b1
3 changed files with 15 additions and 2 deletions
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4
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -1183,9 +1183,9 @@ class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
let Inst{11-15} = DCMX{4-0};
let Inst{16-20} = XB{4-0};
let Inst{21-24} = xo1;
let Inst{25} = DCMX{5};
let Inst{25} = DCMX{6};
let Inst{26-28} = xo2;
let Inst{29} = DCMX{6};
let Inst{29} = DCMX{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}

6
test/MC/Disassembler/PowerPC/vsx.txt
View File

@ -853,3 +853,9 @@
# CHECK: mfvsrld 3, 34
0x7c 0x43 0x02 0x67
# CHECK: xvtstdcdp 63, 63, 65
0xf3 0xe1 0xff 0xeb
# CHECK: xvtstdcsp 63, 63, 34
0xf3 0xe2 0xfe 0xaf

7
test/MC/PowerPC/vsx.s
View File

@ -948,3 +948,10 @@
# CHECK-BE: mfvsrld 3, 34 # encoding: [0x7c,0x43,0x02,0x67]
# CHECK-LE: mfvsrld 3, 34 # encoding: [0x67,0x02,0x43,0x7c]
mfvsrld 3, 34
# CHECK-BE: xvtstdcdp 63, 63, 65 # encoding: [0xf3,0xe1,0xff,0xeb]
# CHECK-LE: xvtstdcdp 63, 63, 65 # encoding: [0xeb,0xff,0xe1,0xf3]
xvtstdcdp 63, 63, 65
# CHECK-BE: xvtstdcsp 63, 63, 34 # encoding: [0xf3,0xe2,0xfe,0xaf]
# CHECK-LE: xvtstdcsp 63, 63, 34 # encoding: [0xaf,0xfe,0xe2,0xf3]
xvtstdcsp 63, 63, 34