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AMDGPU/GlobalISel: Fix broken test

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llvm-svn: 364316
This commit is contained in:
Matt Arsenault 2019-06-25 13:57:53 +00:00
parent 59d186a190
commit 8ee7d4368c
1 changed files with 3 additions and 3 deletions
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6
test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
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@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
# XUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash.
# ERR: remark: <unknown>:0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc)
@ -183,8 +183,8 @@ regBankSelected: true
body: |
bb.0:
; GCN-LABEL: name: implicit_def_s1_scc
; GCN: [[DEF:%[0-9]+]]:scc(s1) = G_IMPLICIT_DEF
; GCN: S_ENDPGM 0, implicit [[DEF]](s1)
; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
; GCN: S_ENDPGM 0, implicit [[DEF]]
%0:scc(s1) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %0
...