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Remove unused but set variables.
llvm-svn: 133347
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@ -2724,7 +2724,6 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
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SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
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SDValue InOp0 = N->getOperand(0);
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EVT InVT = InOp0.getValueType();
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EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
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EVT OutVT = N->getValueType(0);
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EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
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@ -2774,11 +2773,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
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SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
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SDValue InOp0 = N->getOperand(0);
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EVT InVT = InOp0.getValueType();
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EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
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EVT OutVT = N->getValueType(0);
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EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
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assert(NOutVT.isVector() && "This type must be promoted to a vector type");
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@ -2800,10 +2794,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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SDValue InOp0 = N->getOperand(0);
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EVT InVT = InOp0.getValueType();
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EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
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assert(!InVT.isVector() && "Input must not be a scalar");
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assert(!N->getOperand(0).getValueType().isVector() &&
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"Input must be a scalar");
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EVT OutVT = N->getValueType(0);
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EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
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@ -2816,12 +2808,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
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SDValue InOp0 = N->getOperand(0);
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EVT InVT = InOp0.getValueType();
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EVT InElVT = InVT.getVectorElementType();
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EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
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EVT OutVT = N->getValueType(0);
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EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
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assert(NOutVT.isVector() && "This type must be promoted to a vector type");
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@ -2830,7 +2816,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp0);
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SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
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N->getOperand(0));
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SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
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NOutVTElem, N->getOperand(1));
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@ -1833,8 +1833,6 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
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}
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for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
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RegDefPos.IsValid(); RegDefPos.Advance()) {
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EVT VT = RegDefPos.GetValue();
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unsigned RCId, Cost;
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GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
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@ -5587,7 +5587,6 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
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// Create VPADDL node.
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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DebugLoc DL = N->getDebugLoc();
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// Build operand list.
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SmallVector<SDValue, 8> Ops;
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@ -12186,8 +12186,8 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86TargetLowering *XTLI) {
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DebugLoc dl = N->getDebugLoc();
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static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
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const X86TargetLowering *XTLI) {
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SDValue Op0 = N->getOperand(0);
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// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
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// a 32-bit target where SSE doesn't support i64->FP operations.
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@ -12198,7 +12198,8 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86T
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ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
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!XTLI->getSubtarget()->is64Bit() &&
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!DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
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SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
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SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
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Ld->getChain(), Op0, DAG);
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DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
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return FILDChain;
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}
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