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AArch64: Use MachineInstr& in guaranteesZeroRegInBlock(), NFC
llvm-svn: 262143
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@ -63,15 +63,15 @@ char AArch64RedundantCopyElimination::ID = 0;
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INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
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"AArch64 redundant copy elimination pass", false, false)
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static bool guaranteesZeroRegInBlock(MachineInstr *MI, MachineBasicBlock *MBB) {
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unsigned Opc = MI->getOpcode();
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static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
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unsigned Opc = MI.getOpcode();
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// Check if the current basic block is the target block to which the
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// CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
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if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
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MBB == MI->getOperand(1).getMBB())
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MBB == MI.getOperand(1).getMBB())
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return true;
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else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
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MBB != MI->getOperand(1).getMBB())
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MBB != MI.getOperand(1).getMBB())
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return true;
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return false;
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@ -90,12 +90,12 @@ bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
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++CompBr;
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do {
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--CompBr;
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if (guaranteesZeroRegInBlock(CompBr, MBB))
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if (guaranteesZeroRegInBlock(*CompBr, MBB))
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break;
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} while (CompBr != PredMBB->begin() && CompBr->isTerminator());
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// We've not found a CBZ/CBNZ, time to bail out.
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if (!guaranteesZeroRegInBlock(CompBr, MBB))
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if (!guaranteesZeroRegInBlock(*CompBr, MBB))
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return false;
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unsigned TargetReg = CompBr->getOperand(0).getReg();
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