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[ARM] Prevent PerformVDIVCombine from combining a vcvt/vdiv with 8 lanes.

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This would result in a crash since the vcvt used does not support v8i32 types.

llvm-svn: 249560
This commit is contained in:
Chad Rosier 2015-10-07 16:15:40 +00:00
parent 8b3cc14fdc
commit 9072b17685
2 changed files with 12 additions and 3 deletions
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7
lib/Target/ARM/ARMISelLowering.cpp
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@ -9908,10 +9908,12 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
uint32_t FloatBits = FloatTy.getSizeInBits(); uint32_t FloatBits = FloatTy.getSizeInBits();
MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
uint32_t IntBits = IntTy.getSizeInBits(); uint32_t IntBits = IntTy.getSizeInBits();
if (FloatBits != 32 || IntBits > 32) { unsigned NumLanes = Op.getValueType().getVectorNumElements();
if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
// These instructions only exist converting from i32 to f32. We can handle // These instructions only exist converting from i32 to f32. We can handle
// smaller integers by generating an extra extend, but larger ones would // smaller integers by generating an extra extend, but larger ones would
// be lossy. // be lossy. We also can't handle more then 4 lanes, since these intructions
// only support v2i32/v4i32 types.
return SDValue(); return SDValue();
} }
@ -9922,7 +9924,6 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
SDLoc dl(N); SDLoc dl(N);
SDValue ConvInput = Op.getOperand(0); SDValue ConvInput = Op.getOperand(0);
unsigned NumLanes = Op.getValueType().getVectorNumElements();
if (IntBits < FloatBits) if (IntBits < FloatBits)
ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,

8
test/CodeGen/ARM/vdiv_combine.ll
View File

@ -136,3 +136,11 @@ define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
ret <2 x double> %shift ret <2 x double> %shift
} }
; Don't combine with 8 lanes. Just make sure things don't crash.
; CHECK-LABEL: test7
define <8 x float> @test7(<8 x i32> %in) nounwind {
entry:
%vcvt.i = sitofp <8 x i32> %in to <8 x float>
%div.i = fdiv <8 x float> %vcvt.i, <float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0>
ret <8 x float> %div.i
}