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Incorrect check.

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llvm-svn: 37962
This commit is contained in:
Evan Cheng 2007-07-06 23:23:19 +00:00
parent 3b1b3eba6a
commit 92e624a6f7
1 changed files with 2 additions and 4 deletions
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6
lib/Target/ARM/ARMInstrInfo.cpp
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@ -312,8 +312,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() ||
isPredicated(--I) || !isUnpredicatedTerminator(I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastOpc == ARM::B || LastOpc == ARM::tB) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false;
@ -332,8 +331,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineInstr *SecondLastInst = I;
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() &&
!isPredicated(--I) && isUnpredicatedTerminator(I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
return true;
// If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.