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Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.

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llvm-svn: 6618
This commit is contained in:
Misha Brukman 2003-06-05 00:39:45 +00:00
parent bc5ddca6a2
commit 93b1009318
1 changed files with 2 additions and 3 deletions
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5
lib/Target/Sparc/SparcV9_F3.td
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@ -75,14 +75,13 @@ class F3_rdrs1 : F3_rd {
} }
// F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
class F3_rdrs1simm13 : F3_rd { class F3_rdrs1simm13 : F3_rdrs1 {
bits<13> simm13; bits<13> simm13;
set Inst{12-0} = simm13; set Inst{12-0} = simm13;
} }
// F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
class F3_rdrs1rs2 : F3_rs1 { class F3_rdrs1rs2 : F3_rdrs1 {
bits<5> rs2; bits<5> rs2;
set Inst{4-0} = rs2; set Inst{4-0} = rs2;
} }