RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-18 01:35:44 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

Browse Source 
llvm-svn: 134590
This commit is contained in:
Evan Cheng 2011-07-07 03:55:05 +00:00
parent ba39846c2b
commit 952943f744
24 changed files with 161 additions and 150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

140
lib/Target/ARM/ARM.td
View File

@ -21,12 +21,14 @@ include "llvm/Target/Target.td"
// ARM Subtarget features.
//
def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
"Enable VFP2 instructions">;
def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
"Enable VFP3 instructions">;
def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
"Enable NEON instructions">;
def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
"Enable VFP3 instructions",
[FeatureVFP2]>;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable NEON instructions",
[FeatureVFP3]>;
def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
"Enable Thumb2 instructions">;
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
@ -84,33 +86,23 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">;
// ARM architectures.
def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
"ARM v4T">;
def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
"ARM v5T">;
def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
"ARM v5TE, v5TEj, v5TExp">;
def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
"ARM v6">;
def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
"ARM v6m",
[FeatureNoARM, FeatureDB]>;
def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
"ARM v5T",
[HasV4TOps]>;
def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
"ARM v5TE, v5TEj, v5TExp",
[HasV5TOps]>;
def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
"ARM v6",
[HasV5TEOps]>;
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
"ARM v6t2",
[FeatureThumb2, FeatureDSPThumb2]>;
def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
"ARM v7A",
[FeatureThumb2, FeatureNEON, FeatureDB,
FeatureDSPThumb2]>;
def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
"ARM v7M",
[FeatureThumb2, FeatureNoARM, FeatureDB,
FeatureHWDiv]>;
def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
"ARM v7E-M",
[FeatureThumb2, FeatureNoARM, FeatureDB,
FeatureHWDiv, FeatureDSPThumb2,
FeatureT2XtPk]>;
[HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
"ARM v7",
[HasV6T2Ops]>;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@ -145,64 +137,76 @@ def : ProcNoItin<"strongarm1100", []>;
def : ProcNoItin<"strongarm1110", []>;
// V4T Processors.
def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
def : ProcNoItin<"arm710t", [ArchV4T]>;
def : ProcNoItin<"arm720t", [ArchV4T]>;
def : ProcNoItin<"arm9", [ArchV4T]>;
def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
def : ProcNoItin<"arm920", [ArchV4T]>;
def : ProcNoItin<"arm920t", [ArchV4T]>;
def : ProcNoItin<"arm922t", [ArchV4T]>;
def : ProcNoItin<"arm940t", [ArchV4T]>;
def : ProcNoItin<"ep9312", [ArchV4T]>;
def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
def : ProcNoItin<"arm710t", [HasV4TOps]>;
def : ProcNoItin<"arm720t", [HasV4TOps]>;
def : ProcNoItin<"arm9", [HasV4TOps]>;
def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
def : ProcNoItin<"arm920", [HasV4TOps]>;
def : ProcNoItin<"arm920t", [HasV4TOps]>;
def : ProcNoItin<"arm922t", [HasV4TOps]>;
def : ProcNoItin<"arm940t", [HasV4TOps]>;
def : ProcNoItin<"ep9312", [HasV4TOps]>;
// V5T Processors.
def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
def : ProcNoItin<"arm1020t", [ArchV5T]>;
def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
def : ProcNoItin<"arm1020t", [HasV5TOps]>;
// V5TE Processors.
def : ProcNoItin<"arm9e", [ArchV5TE]>;
def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
def : ProcNoItin<"arm10e", [ArchV5TE]>;
def : ProcNoItin<"arm1020e", [ArchV5TE]>;
def : ProcNoItin<"arm1022e", [ArchV5TE]>;
def : ProcNoItin<"xscale", [ArchV5TE]>;
def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
def : ProcNoItin<"arm9e", [HasV5TEOps]>;
def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
def : ProcNoItin<"arm10e", [HasV5TEOps]>;
def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
def : ProcNoItin<"xscale", [HasV5TEOps]>;
def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
// V6 Processors.
def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
// V6M Processors.
def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
FeatureDB]>;
// V6T2 Processors.
def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
// V7 Processors.
// V7a Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
[ArchV7A, ProcA8]>;
[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2]>;
def : Processor<"cortex-a9", CortexA9Itineraries,
[ArchV7A, ProcA9]>;
[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2]>;
def : Processor<"cortex-a9-mp", CortexA9Itineraries,
[ArchV7A, ProcA9, FeatureMP]>;
[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureMP]>;
// V7M Processors.
def : ProcNoItin<"cortex-m3", [ArchV7M]>;
def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
def : ProcNoItin<"cortex-m3", [HasV7Ops,
FeatureThumb2, FeatureNoARM, FeatureDB,
FeatureHWDiv]>;
// V7EM Processors.
def : ProcNoItin<"cortex-m4", [HasV7Ops,
FeatureThumb2, FeatureNoARM, FeatureDB,
FeatureHWDiv, FeatureDSPThumb2,
FeatureT2XtPk, FeatureVFP2,
FeatureVFPOnlySP]>;
//===----------------------------------------------------------------------===//
// Register File Description

17
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -39,9 +39,16 @@ StrictAlign("arm-strict-align", cl::Hidden,
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
: ARMGenSubtargetInfo()
, ARMArchVersion(V4)
, ARMProcFamily(Others)
, ARMFPUType(None)
, HasV4TOps(false)
, HasV5TOps(false)
, HasV5TEOps(false)
, HasV6Ops(false)
, HasV6T2Ops(false)
, HasV7Ops(false)
, HasVFPv2(false)
, HasVFPv3(false)
, HasNEON(false)
, UseNEONForSinglePrecisionFP(false)
, SlowFPVMLx(false)
, HasVMLxForwarding(false)
@ -89,8 +96,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
// ARM version or CPU and then remove this.
if (ARMArchVersion < V6T2 && hasThumb2())
ARMArchVersion = V6T2;
if (!HasV6T2Ops && hasThumb2())
HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString);
@ -104,7 +111,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
if (!isTargetDarwin())
UseMovt = hasV6T2Ops();
else {
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
IsR9Reserved = ReserveR9 | !HasV6Ops;
UseMovt = DarwinUseMOVT && hasV6T2Ops();
}

47
lib/Target/ARM/ARMSubtarget.h
View File

@ -28,27 +28,27 @@ class GlobalValue;
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMArchEnum {
V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM
};
enum ARMProcFamilyEnum {
Others, CortexA8, CortexA9
};
enum ARMFPEnum {
None, VFPv2, VFPv3, NEON
};
/// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
/// V6, V6T2, V7A, V7M, V7EM.
ARMArchEnum ARMArchVersion;
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;
/// ARMFPUType - Floating Point Unit type.
ARMFPEnum ARMFPUType;
/// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
/// Specify whether target support specific ARM ISA variants.
bool HasV4TOps;
bool HasV5TOps;
bool HasV5TEOps;
bool HasV6Ops;
bool HasV6T2Ops;
bool HasV7Ops;
/// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
/// supported.
bool HasVFPv2;
bool HasVFPv3;
bool HasNEON;
/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
/// specified. Use the method useNEONForSinglePrecisionFP() to
@ -172,23 +172,24 @@ protected:
void computeIssueWidth();
bool hasV4TOps() const { return ARMArchVersion >= V4T; }
bool hasV5TOps() const { return ARMArchVersion >= V5T; }
bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
bool hasV6Ops() const { return ARMArchVersion >= V6; }
bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
bool hasV7Ops() const { return ARMArchVersion >= V7A; }
bool hasV4TOps() const { return HasV4TOps; }
bool hasV5TOps() const { return HasV5TOps; }
bool hasV5TEOps() const { return HasV5TEOps; }
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool isCortexA8() const { return ARMProcFamily == CortexA8; }
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
bool hasARMOps() const { return !NoARM; }
bool hasVFP2() const { return ARMFPUType >= VFPv2; }
bool hasVFP3() const { return ARMFPUType >= VFPv3; }
bool hasNEON() const { return ARMFPUType >= NEON; }
bool hasVFP2() const { return HasVFPv2; }
bool hasVFP3() const { return HasVFPv3; }
bool hasNEON() const { return HasNEON; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; }
bool hasDivide() const { return HasHardwareDivide; }
bool hasT2ExtractPack() const { return HasT2ExtractPack; }
bool hasDataBarrier() const { return HasDataBarrier; }

33
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -91,29 +91,28 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
if (Idx) {
unsigned SubVer = TT[Idx];
if (SubVer >= '7' && SubVer <= '9') {
ARMArchFeature = "+v7a";
if (Len >= Idx+2 && TT[Idx+1] == 'm') {
ARMArchFeature = "+v7m";
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv
ARMArchFeature = "+v7,+noarm,+db,+hwdiv";
} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
ARMArchFeature = "+v7em";
}
// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
// FeatureT2XtPk
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk";
} else
// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2
ARMArchFeature = "+v7,+neon,+db,+t2dsp";
} else if (SubVer == '6') {
ARMArchFeature = "+v6";
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
ARMArchFeature = "+v6t2";
}
else
ARMArchFeature = "+v6";
} else if (SubVer == '5') {
ARMArchFeature = "+v5t";
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
ARMArchFeature = "+v5te";
}
} else if (SubVer == '4') {
if (Len >= Idx+2 && TT[Idx+1] == 't') {
ARMArchFeature = "+v4t";
} else {
ARMArchFeature = "";
}
}
else
ARMArchFeature = "+v5t";
} else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
ARMArchFeature = "+v4t";
}
return ARMArchFeature;

2
test/CodeGen/ARM/2009-10-30.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s
; This test checks that the address of the varg arguments is correctly
; computed when there are 5 or more regular arguments.

2
test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
View File

@ -1,7 +1,7 @@
; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s
; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \
; RUN: -mattr=-neon -mattr=+vfp2 \
; RUN: -mattr=-neon,-vfp3,+vfp2 \
; RUN: -arm-reserve-r9 -filetype=obj -o - | \
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s

8
test/CodeGen/ARM/armv4.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB

2
test/CodeGen/ARM/bfx.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s
define i32 @sbfx1(i32 %a) {
; CHECK: sbfx1

4
test/CodeGen/ARM/call.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4
; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
; RUN: llc < %s -mtriple=armv6-linux-gnueabi\
; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]

8
test/CodeGen/ARM/globals.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
@G = external global i32

6
test/CodeGen/ARM/hello.ll
View File

@ -1,8 +1,8 @@
; RUN: llc < %s -march=arm
; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1
; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \
; RUN: grep mov | count 2
; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2
@str = internal constant [12 x i8] c"Hello World\00"

2
test/CodeGen/ARM/iabs.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
;; Integer absolute value, should produce something as good as: ARM:
;; add r3, r0, r0, asr #31

4
test/CodeGen/ARM/ifcvt1.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm
; RUN: llc < %s -march=arm | grep bx | count 1
; RUN: llc < %s -march=arm -mattr=+v4t
; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1
define i32 @t1(i32 %a, i32 %b) {
%tmp2 = icmp eq i32 %a, 0

2
test/CodeGen/ARM/ifcvt2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK: t1:

6
test/CodeGen/ARM/ifcvt3.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=arm
; RUN: llc < %s -march=arm | grep cmpne | count 1
; RUN: llc < %s -march=arm | grep bx | count 2
; RUN: llc < %s -march=arm -mattr=+v4t
; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1
; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
switch i32 %c, label %cond_next [

4
test/CodeGen/ARM/indirectbr.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
@nextaddr = global i8* null ; <i8**> [#uses=2]

2
test/CodeGen/ARM/ldr_frame.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm | not grep mov
; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
define i32 @f1() {
%buf = alloca [32 x i32], align 4

4
test/CodeGen/ARM/phi.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=arm < %s | FileCheck %s
; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s
; <rdar://problem/8686347>
define i32 @test1(i1 %a, i32* %b) {
@ -20,4 +20,4 @@ end:
%r = load i32* %gep
; CHECK-NEXT: bx lr
ret i32 %r
}
}

4
test/CodeGen/ARM/prefetch.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2
; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
; rdar://8601536

4
test/CodeGen/ARM/truncstore-dag-combine.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm | not grep orr
; RUN: llc < %s -march=arm | not grep mov
; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr
; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
define void @bar(i8* %P, i16* %Q) {
entry:

2
test/CodeGen/Thumb/barrier.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M
; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M
declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)

2
test/CodeGen/Thumb2/thumb2-clz.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:

2
test/CodeGen/Thumb2/thumb2-rev.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:

4
test/MC/ARM/prefetch.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2
; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2
; rdar://8924681
define void @t1(i8* %ptr) nounwind {