RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-02 08:26:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.

Browse Source 
For example:
  %1 = lshr i32 %x, 2
  %2 = udiv i32 %1, 100

rdar://12182093

llvm-svn: 162743
This commit is contained in:
Nadav Rotem 2012-08-28 10:01:43 +00:00
parent 6488dc22bb
commit 9582c96aef
3 changed files with 72 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
View File

@ -462,6 +462,16 @@ Instruction *InstCombiner::visitUDiv(BinaryOperator &I) {
}
}
// Udiv ((Lshl x, c1) , c2) -> x / (C1 * 1<<C2);
if (Constant *C = dyn_cast<Constant>(Op1)) {
Value *X = 0, *C1 = 0;
if (match(Op0, m_LShr(m_Value(X), m_Value(C1)))) {
uint64_t NC = cast<ConstantInt>(C)->getZExtValue() *
(1<< cast<ConstantInt>(C1)->getZExtValue());
return BinaryOperator::CreateUDiv(X, ConstantInt::get(I.getType(), NC));
}
}
// X udiv (C1 << N), where C1 is "1<<C2" --> X >> (N+C2)
{ const APInt *CI; Value *N;
if (match(Op1, m_Shl(m_Power2(CI), m_Value(N))) ||
@ -533,6 +543,16 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
ConstantExpr::getNeg(RHS));
}
// Sdiv ((Ashl x, c1) , c2) -> x / (C1 * 1<<C2);
if (Constant *C = dyn_cast<Constant>(Op1)) {
Value *X = 0, *C1 = 0;
if (match(Op0, m_AShr(m_Value(X), m_Value(C1)))) {
uint64_t NC = cast<ConstantInt>(C)->getZExtValue() *
(1<< cast<ConstantInt>(C1)->getZExtValue());
return BinaryOperator::CreateSDiv(X, ConstantInt::get(I.getType(), NC));
}
}
// If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a udiv.
if (I.getType()->isIntegerTy()) {

50
test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll Normal file
View File

@ -0,0 +1,50 @@
; RUN: opt -S -instcombine < %s | FileCheck %s
; rdar://12182093
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
; CHECK: @udiv400
; CHECK: udiv i32 %x, 400
; CHECK: ret
define i32 @udiv400(i32 %x) {
entry:
%div = lshr i32 %x, 2
%div1 = udiv i32 %div, 100
ret i32 %div1
}
; CHECK: @sdiv400
; CHECK: sdiv i32 %x, 400
; CHECK: ret
define i32 @sdiv400(i32 %x) {
entry:
%div = ashr i32 %x, 2
%div1 = sdiv i32 %div, 100
ret i32 %div1
}
; CHECK: @udiv400_no
; CHECK: ashr
; CHECK: div
; CHECK: ret
define i32 @udiv400_no(i32 %x) {
entry:
%div = ashr i32 %x, 2
%div1 = udiv i32 %div, 100
ret i32 %div1
}
; CHECK: @sdiv400_yes
; CHECK: udiv i32 %x, 400
; CHECK: ret
define i32 @sdiv400_yes(i32 %x) {
entry:
%div = lshr i32 %x, 2
; The sign bits of both operands are zero (i.e. we can prove they are
; unsigned inputs), turn this into a udiv.
; Next, optimize this just like sdiv.
%div1 = sdiv i32 %div, 100
ret i32 %div1
}

4
test/Transforms/InstCombine/udiv-simplify-bug-1.ll
View File

@ -6,9 +6,9 @@
; The udiv instructions shouldn't be optimized away, and the
; sext instructions should be optimized to zext.
define i64 @bar(i32 %x) nounwind {
define i64 @bar(i32 %x, i32 %g) nounwind {
%y = lshr i32 %x, 30
%r = udiv i32 %y, 3
%r = udiv i32 %y, %g
%z = sext i32 %r to i64
ret i64 %z
}