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Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.

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llvm-svn: 70950
This commit is contained in:
Evan Cheng 2009-05-05 00:30:09 +00:00
parent ecfc8e8464
commit 95ce4ffb36
4 changed files with 20 additions and 26 deletions
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7
include/llvm/Target/TargetInstrInfo.h
View File

@ -20,6 +20,7 @@
namespace llvm {
class TargetRegisterClass;
class TargetRegisterInfo;
class LiveVariables;
class CalleeSavedInfo;
class SDNode;
@ -505,6 +506,12 @@ public:
virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
};
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrDesc &II, unsigned Op);
} // End llvm namespace
#endif

12
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -418,18 +418,6 @@ void SchedulePostRATDList::FinishBlock() {
ScheduleDAGInstrs::FinishBlock();
}
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands())
return NULL;
if (II.OpInfo[Op].isLookupPtrRegClass())
return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
/// critical path.
static SDep *CriticalPathStep(SUnit *SU) {

14
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -28,20 +28,6 @@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
static const TargetRegisterClass*
getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands()) {
assert(II.isVariadic() && "Invalid operand # of instruction");
return NULL;
}
if (II.OpInfo[Op].isLookupPtrRegClass())
return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
/// implicit physical register output.
void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,

13
lib/Target/TargetInstrInfo.cpp
View File

@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"
using namespace llvm;
@ -35,3 +36,15 @@ bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
return true;
return !isPredicated(MI);
}
/// getInstrOperandRegClass - Return register class of the operand of an
/// instruction of the specified TargetInstrDesc.
const TargetRegisterClass*
llvm::getInstrOperandRegClass(const TargetRegisterInfo *TRI,
const TargetInstrDesc &II, unsigned Op) {
if (Op >= II.getNumOperands())
return NULL;
if (II.OpInfo[Op].isLookupPtrRegClass())
return TRI->getPointerRegClass();
return TRI->getRegClass(II.OpInfo[Op].RegClass);
}