mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-07 11:38:04 +00:00
[AArch64] add more tests for buildvec to shuffle transform; NFC
These are copied from the sibling x86 file. I'm not sure which of the current outputs (if any) is considered optimal, but someone more familiar with AArch may want to take a look. llvm-svn: 351754
This commit is contained in:
Sanjay Patel
parent
0962f23352
commit
965b5f410f
@ -1,6 +1,425 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
|
||||
|
||||
define <2 x i64> @extract0_i32_zext_insert0_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract0_i32_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: zip1 v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 0
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i32_zext_insert0_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract0_i32_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 0
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i32_zext_insert0_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 1
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i32_zext_insert0_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract1_i32_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[1]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 1
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i32_zext_insert0_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract2_i32_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 2
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i32_zext_insert0_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract2_i32_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[2]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 2
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i32_zext_insert0_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract3_i32_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 3
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i32_zext_insert0_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract3_i32_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[3]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 3
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i32_zext_insert1_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract0_i32_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: zip1 v1.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 0
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i32_zext_insert1_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract0_i32_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fmov w8, s0
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 0
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i32_zext_insert1_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract1_i32_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 1
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i32_zext_insert1_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract1_i32_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[1]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 1
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i32_zext_insert1_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract2_i32_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov v0.s[3], wzr
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 2
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i32_zext_insert1_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract2_i32_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[2]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 2
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i32_zext_insert1_i64_undef(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract3_i32_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: movi v1.2d, #0000000000000000
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 3
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i32_zext_insert1_i64_zero(<4 x i32> %x) {
|
||||
; CHECK-LABEL: extract3_i32_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov w8, v0.s[3]
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <4 x i32> %x, i32 3
|
||||
%z = zext i32 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract0_i16_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[0]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: fmov d0, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 0
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract0_i16_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[0]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 0
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract1_i16_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[1]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: fmov d0, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 1
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract1_i16_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[1]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 1
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract2_i16_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[2]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: fmov d0, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 2
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract2_i16_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[2]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 2
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract3_i16_zext_insert0_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[3]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: fmov d0, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 3
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract3_i16_zext_insert0_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[3]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[0], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 3
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract0_i16_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[0]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: dup v0.2d, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 0
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract0_i16_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[0]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 0
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract1_i16_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[1]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: dup v0.2d, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 1
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract1_i16_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[1]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 1
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract2_i16_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[2]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: dup v0.2d, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 2
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract2_i16_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[2]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 2
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract3_i16_zext_insert1_i64_undef:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[3]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: dup v0.2d, x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 3
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> undef, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) {
|
||||
; CHECK-LABEL: extract3_i16_zext_insert1_i64_zero:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umov w8, v0.h[3]
|
||||
; CHECK-NEXT: and x8, x8, #0xffff
|
||||
; CHECK-NEXT: movi v0.2d, #0000000000000000
|
||||
; CHECK-NEXT: mov v0.d[1], x8
|
||||
; CHECK-NEXT: ret
|
||||
%e = extractelement <8 x i16> %x, i32 3
|
||||
%z = zext i16 %e to i64
|
||||
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
|
||||
ret <2 x i64> %r
|
||||
}
|
||||
|
||||
; This would crash because we did not expect to create
|
||||
; a shuffle for a vector where the source operand is
|
||||
; not the same size as the result.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user