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[X86] Remove special handling for 16 bit for A asm constraints.

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Our 16 bit support is assembler-only + the terrible hack that is
.code16gcc. Simply using 32 bit registers does the right thing for the
latter.

Fixes PR32681.

llvm-svn: 300429
This commit is contained in:
Benjamin Kramer 2017-04-16 20:13:08 +00:00
parent 80f276ac53
commit 96ee5e4899
3 changed files with 11 additions and 8 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -35922,14 +35922,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Subtarget.is64Bit()) {
Res.first = X86::RAX;
Res.second = &X86::GR64_ADRegClass;
} else if (Subtarget.is32Bit()) {
} else {
assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
"Expecting 64, 32 or 16 bit subtarget");
Res.first = X86::EAX;
Res.second = &X86::GR32_ADRegClass;
} else if (Subtarget.is16Bit()) {
Res.first = X86::AX;
Res.second = &X86::GR16_ADRegClass;
} else {
llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
}
return Res;
}

1
lib/Target/X86/X86RegisterInfo.td
View File

@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
(add LOW32_ADDR_ACCESS, RBP)>;
// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;

9
test/CodeGen/X86/x86-16.ll
View File

@ -12,9 +12,16 @@ define i32 @main() #0 {
; CHECK: .code16
; CHECK-LABEL: main
define i64 @foo(i32 %index) #0 {
%asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
ret i64 %asm
}
; CHECK-LABEL: foo
; CHECK: rdmsr
attributes #0 = { nounwind }
!llvm.ident = !{!0}
!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}
!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}