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Fix (bitcast (fabs x)), (bitcast (fneg x)) and (bitcast (fcopysign cst,
x)) combines for ppc_fp128, since signbit computation is more complicated. Discussion thread: http://lists.llvm.org/pipermail/llvm-dev/2015-November/092863.html Patch by Tim Shen! llvm-svn: 255305
This commit is contained in:
Eric Christopher
parent
486717bbd5
commit
971f116a1c
@ -7244,6 +7244,12 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
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return SDValue();
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}
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static unsigned getPPCf128HiElementSelector(const SelectionDAG &DAG) {
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// On little-endian machines, bitcasting from ppcf128 to i128 does swap the Hi
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// and Lo parts; on big-endian machines it doesn't.
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return DAG.getDataLayout().isBigEndian() ? 1 : 0;
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}
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SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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@ -7310,6 +7316,14 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
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// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
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//
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// For ppc_fp128:
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// fold (bitcast (fneg x)) ->
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// flipbit = signbit
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// (xor (bitcast x) (build_pair flipbit, flipbit))
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// fold (bitcast (fabs x)) ->
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// flipbit = (and (extract_element (bitcast x), 0), signbit)
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// (xor (bitcast x) (build_pair flipbit, flipbit))
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// This often reduces constant pool loads.
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if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
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(N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
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@ -7320,6 +7334,29 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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AddToWorklist(NewConv.getNode());
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SDLoc DL(N);
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if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
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assert(VT.getSizeInBits() == 128);
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SDValue SignBit = DAG.getConstant(
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APInt::getSignBit(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
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SDValue FlipBit;
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if (N0.getOpcode() == ISD::FNEG) {
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FlipBit = SignBit;
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AddToWorklist(FlipBit.getNode());
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} else {
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assert(N0.getOpcode() == ISD::FABS);
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SDValue Hi =
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DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(NewConv), MVT::i64, NewConv,
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DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG),
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SDLoc(NewConv)));
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AddToWorklist(Hi.getNode());
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FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);
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AddToWorklist(FlipBit.getNode());
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}
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SDValue FlipBits =
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DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
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AddToWorklist(FlipBits.getNode());
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return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits);
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}
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
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if (N0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::XOR, DL, VT,
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@ -7333,6 +7370,13 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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// (or (and (bitconvert x), sign), (and cst, (not sign)))
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// Note that we don't handle (copysign x, cst) because this can always be
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// folded to an fneg or fabs.
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//
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// For ppc_fp128:
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// fold (bitcast (fcopysign cst, x)) ->
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// flipbit = (and (extract_element
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// (xor (bitcast cst), (bitcast x)), 0),
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// signbit)
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// (xor (bitcast cst) (build_pair flipbit, flipbit))
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if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
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isa<ConstantFPSDNode>(N0.getOperand(0)) &&
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VT.isInteger() && !VT.isVector()) {
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@ -7361,6 +7405,30 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
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AddToWorklist(X.getNode());
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}
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if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits() / 2);
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SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0.getOperand(0)), VT,
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N0.getOperand(0));
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AddToWorklist(Cst.getNode());
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SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0.getOperand(1)), VT,
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N0.getOperand(1));
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AddToWorklist(X.getNode());
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SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X);
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AddToWorklist(XorResult.getNode());
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SDValue XorResult64 = DAG.getNode(
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ISD::EXTRACT_ELEMENT, SDLoc(XorResult), MVT::i64, XorResult,
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DAG.getIntPtrConstant(getPPCf128HiElementSelector(DAG),
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SDLoc(XorResult)));
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AddToWorklist(XorResult64.getNode());
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SDValue FlipBit =
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DAG.getNode(ISD::AND, SDLoc(XorResult64), MVT::i64, XorResult64,
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DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64));
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AddToWorklist(FlipBit.getNode());
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SDValue FlipBits =
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DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
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AddToWorklist(FlipBits.getNode());
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return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits);
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}
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APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
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X = DAG.getNode(ISD::AND, SDLoc(X), VT,
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X, DAG.getConstant(SignBit, SDLoc(X), VT));
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103
test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
Normal file
103
test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
Normal file
@ -0,0 +1,103 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
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define i128 @test_abs(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_abs:
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; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
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; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
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; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
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; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
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; PPC64-DAG: li [[MASK_REG:[0-9]+]], 1
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; PPC64: sldi [[MASK_REG]], [[MASK_REG]], 63
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; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
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; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
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; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]]
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; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64: blr
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; PPC32-DAG: stfd 1, 24(1)
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; PPC32-DAG: stfd 2, 16(1)
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; PPC32: nop
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; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
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; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
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; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
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; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
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; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI0]], 0, 0, 0
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; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]]
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; PPC32-DAG: xor [[LO0]], [[LO0]], [[FLIP_BIT]]
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; PPC32: blr
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%0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x)
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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define i128 @test_neg(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_neg:
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; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
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; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
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; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
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; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
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; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
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; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
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; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
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; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
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; PPC64-NOT: BARRIER
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; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
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; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
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; PPC64: blr
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; PPC32-DAG: stfd 1, 24(1)
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; PPC32-DAG: stfd 2, 16(1)
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; PPC32: nop
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; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
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; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
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; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
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; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
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; PPC32-NOT: BARRIER
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; PPC32-DAG: xoris [[HI0]], [[HI0]], 32768
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; PPC32-DAG: xoris [[LO0]], [[LO0]], 32768
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; PPC32: blr
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%0 = fsub ppc_fp128 0xM80000000000000000000000000000000, %x
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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define i128 @test_copysign(ppc_fp128 %x) nounwind {
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entry:
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; PPC64-LABEL: test_copysign:
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; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]]
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; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
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; PPC64-DAG: li [[SIGN:[0-9]+]], 1
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; PPC64-DAG: sldi [[SIGN]], [[SIGN]], 63
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; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
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; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
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; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
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; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
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; PPC64-NOT: BARRIER
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; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
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; PPC64-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]]
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; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
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; PPC64-DAG: xor 4, [[SIGN]], [[CST_LO]]
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; PPC64: blr
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; PPC32: stfd 1, [[STACK:[0-9]+]](1)
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; PPC32: nop
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; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
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; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
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; PPC32-NOT: BARRIER
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; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399
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; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304
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; PPC32: blr
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%0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xMBCB0000000000000400F000000000000, ppc_fp128 %x)
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%1 = bitcast ppc_fp128 %0 to i128
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ret i128 %1
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}
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declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128)
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declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128)
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