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[PowerPC] Set setMaxAtomicSizeInBitsSupported appropriately for 32-bit PowerPC in PPCTargetLowering
Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D86165
This commit is contained in:
Brad Smith
parent
621df3de9a
commit
99286ab2f0
@ -1199,6 +1199,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setLibcallName(RTLIB::SRA_I128, nullptr);
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}
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if (!isPPC64)
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setMaxAtomicSizeInBitsSupported(32);
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setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
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// We have target-specific dag combine patterns for the following nodes:
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
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; This is already checked for in Atomics-64.ll
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@ -8,9 +9,25 @@
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; Indexed version of loads
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define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: load_x_i8_seq_cst
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; CHECK: sync
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; CHECK: lbzx [[VAL:r[0-9]+]]
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; PPC32-LABEL: load_x_i8_seq_cst:
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; PPC32: # %bb.0:
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; PPC32-NEXT: lis r4, 1
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; PPC32-NEXT: sync
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; PPC32-NEXT: ori r4, r4, 24464
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; PPC32-NEXT: lbzx r3, r3, r4
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; PPC32-NEXT: lwsync
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i8_seq_cst:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 1
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; PPC64-NEXT: sync
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; PPC64-NEXT: ori r4, r4, 24464
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; PPC64-NEXT: lbzx r3, r3, r4
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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; CHECK-PPC64: bne- [[CR]], .+4
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@ -20,8 +37,23 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
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ret i8 %val
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}
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define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
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; CHECK-LABEL: load_x_i16_acquire
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; CHECK: lhzx [[VAL:r[0-9]+]]
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; PPC32-LABEL: load_x_i16_acquire:
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; PPC32: # %bb.0:
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; PPC32-NEXT: lis r4, 2
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; PPC32-NEXT: ori r4, r4, 48928
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; PPC32-NEXT: lhzx r3, r3, r4
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; PPC32-NEXT: lwsync
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i16_acquire:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 2
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; PPC64-NEXT: ori r4, r4, 48928
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; PPC64-NEXT: lhzx r3, r3, r4
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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; CHECK-PPC64: bne- [[CR]], .+4
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@ -31,19 +63,39 @@ define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
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ret i16 %val
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}
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define i32 @load_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: load_x_i32_monotonic
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; CHECK: lwzx
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; CHECK-NOT: sync
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; CHECK-LABEL: load_x_i32_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 5
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; CHECK-NEXT: ori r4, r4, 32320
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; CHECK-NEXT: lwzx r3, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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%val = load atomic i32, i32* %ptr monotonic, align 4
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ret i32 %val
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}
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define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: load_x_i64_unordered
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: ldx
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; CHECK-NOT: sync
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; PPC32-LABEL: load_x_i64_unordered:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stw r0, 4(r1)
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: addi r3, r3, -896
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; PPC32-NEXT: addis r3, r3, 11
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; PPC32-NEXT: li r4, 0
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; PPC32-NEXT: bl __atomic_load_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i64_unordered:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 10
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; PPC64-NEXT: ori r4, r4, 64640
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; PPC64-NEXT: ldx r3, r3, r4
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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%val = load atomic i64, i64* %ptr unordered, align 8
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ret i64 %val
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@ -51,35 +103,69 @@ define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
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; Indexed version of stores
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define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: store_x_i8_seq_cst
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; CHECK: sync
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; CHECK: stbx
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; CHECK-LABEL: store_x_i8_seq_cst:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 1
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; CHECK-NEXT: ori r4, r4, 24464
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: sync
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; CHECK-NEXT: stbx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
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store atomic i8 42, i8* %ptr seq_cst, align 1
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ret void
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}
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define void @store_x_i16_release([100000 x i16]* %mem) {
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; CHECK-LABEL: store_x_i16_release
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; CHECK: lwsync
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; CHECK: sthx
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; CHECK-LABEL: store_x_i16_release:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 2
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; CHECK-NEXT: ori r4, r4, 48928
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: sthx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
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store atomic i16 42, i16* %ptr release, align 2
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ret void
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}
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define void @store_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: store_x_i32_monotonic
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; CHECK-NOT: sync
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; CHECK: stwx
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; CHECK-LABEL: store_x_i32_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 5
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; CHECK-NEXT: ori r4, r4, 32320
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: stwx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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store atomic i32 42, i32* %ptr monotonic, align 4
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ret void
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}
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define void @store_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: store_x_i64_unordered
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; CHECK-NOT: sync
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: stdx
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; PPC32-LABEL: store_x_i64_unordered:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stw r0, 4(r1)
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: addi r3, r3, -896
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; PPC32-NEXT: addis r3, r3, 11
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; PPC32-NEXT: li r5, 0
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; PPC32-NEXT: li r6, 42
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; PPC32-NEXT: li r7, 0
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; PPC32-NEXT: bl __atomic_store_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: store_x_i64_unordered:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 10
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; PPC64-NEXT: ori r4, r4, 64640
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; PPC64-NEXT: li r5, 42
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; PPC64-NEXT: stdx r5, r3, r4
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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store atomic i64 42, i64* %ptr unordered, align 8
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ret void
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; This is already checked for in Atomics-64.ll
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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@ -9,22 +10,35 @@
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; We first check loads, for all sizes from i8 to i64.
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; We also vary orderings to check for barriers.
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define i8 @load_i8_unordered(i8* %mem) {
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; CHECK-LABEL: load_i8_unordered
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; CHECK: lbz
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; CHECK-NOT: sync
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; CHECK-LABEL: load_i8_unordered:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lbz r3, 0(r3)
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; CHECK-NEXT: blr
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%val = load atomic i8, i8* %mem unordered, align 1
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ret i8 %val
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}
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define i16 @load_i16_monotonic(i16* %mem) {
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; CHECK-LABEL: load_i16_monotonic
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; CHECK: lhz
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; CHECK-NOT: sync
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; CHECK-LABEL: load_i16_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lhz r3, 0(r3)
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; CHECK-NEXT: blr
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%val = load atomic i16, i16* %mem monotonic, align 2
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ret i16 %val
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}
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define i32 @load_i32_acquire(i32* %mem) {
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; CHECK-LABEL: load_i32_acquire
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; CHECK: lwz [[VAL:r[0-9]+]]
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; PPC32-LABEL: load_i32_acquire:
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; PPC32: # %bb.0:
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; PPC32-NEXT: lwz r3, 0(r3)
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; PPC32-NEXT: lwsync
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_i32_acquire:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lwz r3, 0(r3)
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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%val = load atomic i32, i32* %mem acquire, align 4
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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@ -33,11 +47,28 @@ define i32 @load_i32_acquire(i32* %mem) {
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ret i32 %val
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}
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define i64 @load_i64_seq_cst(i64* %mem) {
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; CHECK-LABEL: load_i64_seq_cst
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; CHECK: sync
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: ld [[VAL:r[0-9]+]]
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; PPC32-LABEL: load_i64_seq_cst:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stw r0, 4(r1)
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: li r4, 5
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; PPC32-NEXT: bl __atomic_load_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_i64_seq_cst:
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; PPC64: # %bb.0:
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; PPC64-NEXT: sync
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; PPC64-NEXT: ld r3, 0(r3)
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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%val = load atomic i64, i64* %mem seq_cst, align 8
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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@ -48,95 +79,401 @@ define i64 @load_i64_seq_cst(i64* %mem) {
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; Stores
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define void @store_i8_unordered(i8* %mem) {
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; CHECK-LABEL: store_i8_unordered
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; CHECK-NOT: sync
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; CHECK: stb
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; CHECK-LABEL: store_i8_unordered:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li r4, 42
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; CHECK-NEXT: stb r4, 0(r3)
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; CHECK-NEXT: blr
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store atomic i8 42, i8* %mem unordered, align 1
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ret void
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}
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define void @store_i16_monotonic(i16* %mem) {
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; CHECK-LABEL: store_i16_monotonic
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; CHECK-NOT: sync
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; CHECK: sth
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; CHECK-LABEL: store_i16_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li r4, 42
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; CHECK-NEXT: sth r4, 0(r3)
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; CHECK-NEXT: blr
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store atomic i16 42, i16* %mem monotonic, align 2
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ret void
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}
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define void @store_i32_release(i32* %mem) {
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; CHECK-LABEL: store_i32_release
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; CHECK: lwsync
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; CHECK: stw
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; CHECK-LABEL: store_i32_release:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li r4, 42
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: stw r4, 0(r3)
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; CHECK-NEXT: blr
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store atomic i32 42, i32* %mem release, align 4
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ret void
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}
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define void @store_i64_seq_cst(i64* %mem) {
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; CHECK-LABEL: store_i64_seq_cst
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; CHECK: sync
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: std
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; PPC32-LABEL: store_i64_seq_cst:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stw r0, 4(r1)
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: li r5, 0
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; PPC32-NEXT: li r6, 42
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; PPC32-NEXT: li r7, 5
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; PPC32-NEXT: bl __atomic_store_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: store_i64_seq_cst:
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; PPC64: # %bb.0:
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; PPC64-NEXT: li r4, 42
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; PPC64-NEXT: sync
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; PPC64-NEXT: std r4, 0(r3)
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; PPC64-NEXT: blr
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store atomic i64 42, i64* %mem seq_cst, align 8
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ret void
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}
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; Atomic CmpXchg
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define i8 @cas_strong_i8_sc_sc(i8* %mem) {
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; CHECK-LABEL: cas_strong_i8_sc_sc
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; CHECK: sync
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; PPC32-LABEL: cas_strong_i8_sc_sc:
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; PPC32: # %bb.0:
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; PPC32-NEXT: rlwinm r8, r3, 3, 27, 28
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; PPC32-NEXT: li r5, 1
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; PPC32-NEXT: li r6, 0
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; PPC32-NEXT: li r7, 255
|
||||
; PPC32-NEXT: rlwinm r4, r3, 0, 0, 29
|
||||
; PPC32-NEXT: xori r3, r8, 24
|
||||
; PPC32-NEXT: slw r5, r5, r3
|
||||
; PPC32-NEXT: slw r8, r6, r3
|
||||
; PPC32-NEXT: slw r6, r7, r3
|
||||
; PPC32-NEXT: and r7, r5, r6
|
||||
; PPC32-NEXT: and r8, r8, r6
|
||||
; PPC32-NEXT: sync
|
||||
; PPC32-NEXT: .LBB8_1:
|
||||
; PPC32-NEXT: lwarx r9, 0, r4
|
||||
; PPC32-NEXT: and r5, r9, r6
|
||||
; PPC32-NEXT: cmpw r5, r8
|
||||
; PPC32-NEXT: bne cr0, .LBB8_3
|
||||
; PPC32-NEXT: # %bb.2:
|
||||
; PPC32-NEXT: andc r9, r9, r6
|
||||
; PPC32-NEXT: or r9, r9, r7
|
||||
; PPC32-NEXT: stwcx. r9, 0, r4
|
||||
; PPC32-NEXT: bne cr0, .LBB8_1
|
||||
; PPC32-NEXT: b .LBB8_4
|
||||
; PPC32-NEXT: .LBB8_3:
|
||||
; PPC32-NEXT: stwcx. r9, 0, r4
|
||||
; PPC32-NEXT: .LBB8_4:
|
||||
; PPC32-NEXT: srw r3, r5, r3
|
||||
; PPC32-NEXT: lwsync
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: cas_strong_i8_sc_sc:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: rlwinm r8, r3, 3, 27, 28
|
||||
; PPC64-NEXT: li r5, 1
|
||||
; PPC64-NEXT: li r6, 0
|
||||
; PPC64-NEXT: li r7, 255
|
||||
; PPC64-NEXT: rldicr r4, r3, 0, 61
|
||||
; PPC64-NEXT: xori r3, r8, 24
|
||||
; PPC64-NEXT: slw r5, r5, r3
|
||||
; PPC64-NEXT: slw r8, r6, r3
|
||||
; PPC64-NEXT: slw r6, r7, r3
|
||||
; PPC64-NEXT: and r7, r5, r6
|
||||
; PPC64-NEXT: and r8, r8, r6
|
||||
; PPC64-NEXT: sync
|
||||
; PPC64-NEXT: .LBB8_1:
|
||||
; PPC64-NEXT: lwarx r9, 0, r4
|
||||
; PPC64-NEXT: and r5, r9, r6
|
||||
; PPC64-NEXT: cmpw r5, r8
|
||||
; PPC64-NEXT: bne cr0, .LBB8_3
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: andc r9, r9, r6
|
||||
; PPC64-NEXT: or r9, r9, r7
|
||||
; PPC64-NEXT: stwcx. r9, 0, r4
|
||||
; PPC64-NEXT: bne cr0, .LBB8_1
|
||||
; PPC64-NEXT: b .LBB8_4
|
||||
; PPC64-NEXT: .LBB8_3:
|
||||
; PPC64-NEXT: stwcx. r9, 0, r4
|
||||
; PPC64-NEXT: .LBB8_4:
|
||||
; PPC64-NEXT: srw r3, r5, r3
|
||||
; PPC64-NEXT: lwsync
|
||||
; PPC64-NEXT: blr
|
||||
%val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst
|
||||
; CHECK: lwsync
|
||||
%loaded = extractvalue { i8, i1} %val, 0
|
||||
ret i8 %loaded
|
||||
}
|
||||
define i16 @cas_weak_i16_acquire_acquire(i16* %mem) {
|
||||
; CHECK-LABEL: cas_weak_i16_acquire_acquire
|
||||
;CHECK-NOT: sync
|
||||
; PPC32-LABEL: cas_weak_i16_acquire_acquire:
|
||||
; PPC32: # %bb.0:
|
||||
; PPC32-NEXT: li r6, 0
|
||||
; PPC32-NEXT: rlwinm r4, r3, 3, 27, 27
|
||||
; PPC32-NEXT: li r5, 1
|
||||
; PPC32-NEXT: ori r7, r6, 65535
|
||||
; PPC32-NEXT: xori r4, r4, 16
|
||||
; PPC32-NEXT: slw r8, r5, r4
|
||||
; PPC32-NEXT: slw r9, r6, r4
|
||||
; PPC32-NEXT: slw r5, r7, r4
|
||||
; PPC32-NEXT: rlwinm r3, r3, 0, 0, 29
|
||||
; PPC32-NEXT: and r6, r8, r5
|
||||
; PPC32-NEXT: and r8, r9, r5
|
||||
; PPC32-NEXT: .LBB9_1:
|
||||
; PPC32-NEXT: lwarx r9, 0, r3
|
||||
; PPC32-NEXT: and r7, r9, r5
|
||||
; PPC32-NEXT: cmpw r7, r8
|
||||
; PPC32-NEXT: bne cr0, .LBB9_3
|
||||
; PPC32-NEXT: # %bb.2:
|
||||
; PPC32-NEXT: andc r9, r9, r5
|
||||
; PPC32-NEXT: or r9, r9, r6
|
||||
; PPC32-NEXT: stwcx. r9, 0, r3
|
||||
; PPC32-NEXT: bne cr0, .LBB9_1
|
||||
; PPC32-NEXT: b .LBB9_4
|
||||
; PPC32-NEXT: .LBB9_3:
|
||||
; PPC32-NEXT: stwcx. r9, 0, r3
|
||||
; PPC32-NEXT: .LBB9_4:
|
||||
; PPC32-NEXT: srw r3, r7, r4
|
||||
; PPC32-NEXT: lwsync
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: cas_weak_i16_acquire_acquire:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: li r6, 0
|
||||
; PPC64-NEXT: rlwinm r4, r3, 3, 27, 27
|
||||
; PPC64-NEXT: li r5, 1
|
||||
; PPC64-NEXT: ori r7, r6, 65535
|
||||
; PPC64-NEXT: xori r4, r4, 16
|
||||
; PPC64-NEXT: slw r8, r5, r4
|
||||
; PPC64-NEXT: slw r9, r6, r4
|
||||
; PPC64-NEXT: slw r5, r7, r4
|
||||
; PPC64-NEXT: rldicr r3, r3, 0, 61
|
||||
; PPC64-NEXT: and r6, r8, r5
|
||||
; PPC64-NEXT: and r8, r9, r5
|
||||
; PPC64-NEXT: .LBB9_1:
|
||||
; PPC64-NEXT: lwarx r9, 0, r3
|
||||
; PPC64-NEXT: and r7, r9, r5
|
||||
; PPC64-NEXT: cmpw r7, r8
|
||||
; PPC64-NEXT: bne cr0, .LBB9_3
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: andc r9, r9, r5
|
||||
; PPC64-NEXT: or r9, r9, r6
|
||||
; PPC64-NEXT: stwcx. r9, 0, r3
|
||||
; PPC64-NEXT: bne cr0, .LBB9_1
|
||||
; PPC64-NEXT: b .LBB9_4
|
||||
; PPC64-NEXT: .LBB9_3:
|
||||
; PPC64-NEXT: stwcx. r9, 0, r3
|
||||
; PPC64-NEXT: .LBB9_4:
|
||||
; PPC64-NEXT: srw r3, r7, r4
|
||||
; PPC64-NEXT: lwsync
|
||||
; PPC64-NEXT: blr
|
||||
%val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire
|
||||
; CHECK: lwsync
|
||||
%loaded = extractvalue { i16, i1} %val, 0
|
||||
ret i16 %loaded
|
||||
}
|
||||
define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) {
|
||||
; CHECK-LABEL: cas_strong_i32_acqrel_acquire
|
||||
; CHECK: lwsync
|
||||
; CHECK-LABEL: cas_strong_i32_acqrel_acquire:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: li r5, 1
|
||||
; CHECK-NEXT: li r6, 0
|
||||
; CHECK-NEXT: lwsync
|
||||
; CHECK-NEXT: .LBB10_1:
|
||||
; CHECK-NEXT: lwarx r4, 0, r3
|
||||
; CHECK-NEXT: cmpw r6, r4
|
||||
; CHECK-NEXT: bne cr0, .LBB10_3
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: stwcx. r5, 0, r3
|
||||
; CHECK-NEXT: bne cr0, .LBB10_1
|
||||
; CHECK-NEXT: b .LBB10_4
|
||||
; CHECK-NEXT: .LBB10_3:
|
||||
; CHECK-NEXT: stwcx. r4, 0, r3
|
||||
; CHECK-NEXT: .LBB10_4:
|
||||
; CHECK-NEXT: mr r3, r4
|
||||
; CHECK-NEXT: lwsync
|
||||
; CHECK-NEXT: blr
|
||||
%val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
|
||||
; CHECK: lwsync
|
||||
%loaded = extractvalue { i32, i1} %val, 0
|
||||
ret i32 %loaded
|
||||
}
|
||||
define i64 @cas_weak_i64_release_monotonic(i64* %mem) {
|
||||
; CHECK-LABEL: cas_weak_i64_release_monotonic
|
||||
; CHECK: lwsync
|
||||
; PPC32-LABEL: cas_weak_i64_release_monotonic:
|
||||
; PPC32: # %bb.0:
|
||||
; PPC32-NEXT: mflr r0
|
||||
; PPC32-NEXT: stw r0, 4(r1)
|
||||
; PPC32-NEXT: stwu r1, -16(r1)
|
||||
; PPC32-NEXT: .cfi_def_cfa_offset 16
|
||||
; PPC32-NEXT: .cfi_offset lr, 4
|
||||
; PPC32-NEXT: li r4, 0
|
||||
; PPC32-NEXT: stw r4, 12(r1)
|
||||
; PPC32-NEXT: li r5, 0
|
||||
; PPC32-NEXT: stw r4, 8(r1)
|
||||
; PPC32-NEXT: addi r4, r1, 8
|
||||
; PPC32-NEXT: li r6, 1
|
||||
; PPC32-NEXT: li r7, 3
|
||||
; PPC32-NEXT: li r8, 0
|
||||
; PPC32-NEXT: bl __atomic_compare_exchange_8
|
||||
; PPC32-NEXT: lwz r4, 12(r1)
|
||||
; PPC32-NEXT: lwz r3, 8(r1)
|
||||
; PPC32-NEXT: lwz r0, 20(r1)
|
||||
; PPC32-NEXT: addi r1, r1, 16
|
||||
; PPC32-NEXT: mtlr r0
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: cas_weak_i64_release_monotonic:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: li r5, 1
|
||||
; PPC64-NEXT: li r6, 0
|
||||
; PPC64-NEXT: lwsync
|
||||
; PPC64-NEXT: .LBB11_1:
|
||||
; PPC64-NEXT: ldarx r4, 0, r3
|
||||
; PPC64-NEXT: cmpd r6, r4
|
||||
; PPC64-NEXT: bne cr0, .LBB11_4
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: stdcx. r5, 0, r3
|
||||
; PPC64-NEXT: bne cr0, .LBB11_1
|
||||
; PPC64-NEXT: # %bb.3:
|
||||
; PPC64-NEXT: mr r3, r4
|
||||
; PPC64-NEXT: blr
|
||||
; PPC64-NEXT: .LBB11_4:
|
||||
; PPC64-NEXT: stdcx. r4, 0, r3
|
||||
; PPC64-NEXT: mr r3, r4
|
||||
; PPC64-NEXT: blr
|
||||
%val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic
|
||||
; CHECK-NOT: [sync ]
|
||||
%loaded = extractvalue { i64, i1} %val, 0
|
||||
ret i64 %loaded
|
||||
}
|
||||
|
||||
; AtomicRMW
|
||||
define i8 @add_i8_monotonic(i8* %mem, i8 %operand) {
|
||||
; CHECK-LABEL: add_i8_monotonic
|
||||
; CHECK-NOT: sync
|
||||
; PPC32-LABEL: add_i8_monotonic:
|
||||
; PPC32: # %bb.0:
|
||||
; PPC32-NEXT: rlwinm r7, r3, 3, 27, 28
|
||||
; PPC32-NEXT: li r6, 255
|
||||
; PPC32-NEXT: rlwinm r5, r3, 0, 0, 29
|
||||
; PPC32-NEXT: xori r3, r7, 24
|
||||
; PPC32-NEXT: slw r4, r4, r3
|
||||
; PPC32-NEXT: slw r6, r6, r3
|
||||
; PPC32-NEXT: .LBB12_1:
|
||||
; PPC32-NEXT: lwarx r7, 0, r5
|
||||
; PPC32-NEXT: add r8, r4, r7
|
||||
; PPC32-NEXT: andc r9, r7, r6
|
||||
; PPC32-NEXT: and r8, r8, r6
|
||||
; PPC32-NEXT: or r8, r8, r9
|
||||
; PPC32-NEXT: stwcx. r8, 0, r5
|
||||
; PPC32-NEXT: bne cr0, .LBB12_1
|
||||
; PPC32-NEXT: # %bb.2:
|
||||
; PPC32-NEXT: srw r3, r7, r3
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: add_i8_monotonic:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: rlwinm r7, r3, 3, 27, 28
|
||||
; PPC64-NEXT: li r6, 255
|
||||
; PPC64-NEXT: rldicr r5, r3, 0, 61
|
||||
; PPC64-NEXT: xori r3, r7, 24
|
||||
; PPC64-NEXT: slw r4, r4, r3
|
||||
; PPC64-NEXT: slw r6, r6, r3
|
||||
; PPC64-NEXT: .LBB12_1:
|
||||
; PPC64-NEXT: lwarx r7, 0, r5
|
||||
; PPC64-NEXT: add r8, r4, r7
|
||||
; PPC64-NEXT: andc r9, r7, r6
|
||||
; PPC64-NEXT: and r8, r8, r6
|
||||
; PPC64-NEXT: or r8, r8, r9
|
||||
; PPC64-NEXT: stwcx. r8, 0, r5
|
||||
; PPC64-NEXT: bne cr0, .LBB12_1
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: srw r3, r7, r3
|
||||
; PPC64-NEXT: blr
|
||||
%val = atomicrmw add i8* %mem, i8 %operand monotonic
|
||||
ret i8 %val
|
||||
}
|
||||
define i16 @xor_i16_seq_cst(i16* %mem, i16 %operand) {
|
||||
; CHECK-LABEL: xor_i16_seq_cst
|
||||
; CHECK: sync
|
||||
; PPC32-LABEL: xor_i16_seq_cst:
|
||||
; PPC32: # %bb.0:
|
||||
; PPC32-NEXT: li r6, 0
|
||||
; PPC32-NEXT: rlwinm r7, r3, 3, 27, 27
|
||||
; PPC32-NEXT: rlwinm r5, r3, 0, 0, 29
|
||||
; PPC32-NEXT: ori r6, r6, 65535
|
||||
; PPC32-NEXT: xori r3, r7, 16
|
||||
; PPC32-NEXT: slw r4, r4, r3
|
||||
; PPC32-NEXT: slw r6, r6, r3
|
||||
; PPC32-NEXT: sync
|
||||
; PPC32-NEXT: .LBB13_1:
|
||||
; PPC32-NEXT: lwarx r7, 0, r5
|
||||
; PPC32-NEXT: xor r8, r4, r7
|
||||
; PPC32-NEXT: andc r9, r7, r6
|
||||
; PPC32-NEXT: and r8, r8, r6
|
||||
; PPC32-NEXT: or r8, r8, r9
|
||||
; PPC32-NEXT: stwcx. r8, 0, r5
|
||||
; PPC32-NEXT: bne cr0, .LBB13_1
|
||||
; PPC32-NEXT: # %bb.2:
|
||||
; PPC32-NEXT: srw r3, r7, r3
|
||||
; PPC32-NEXT: lwsync
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: xor_i16_seq_cst:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: li r6, 0
|
||||
; PPC64-NEXT: rlwinm r7, r3, 3, 27, 27
|
||||
; PPC64-NEXT: rldicr r5, r3, 0, 61
|
||||
; PPC64-NEXT: ori r6, r6, 65535
|
||||
; PPC64-NEXT: xori r3, r7, 16
|
||||
; PPC64-NEXT: slw r4, r4, r3
|
||||
; PPC64-NEXT: slw r6, r6, r3
|
||||
; PPC64-NEXT: sync
|
||||
; PPC64-NEXT: .LBB13_1:
|
||||
; PPC64-NEXT: lwarx r7, 0, r5
|
||||
; PPC64-NEXT: xor r8, r4, r7
|
||||
; PPC64-NEXT: andc r9, r7, r6
|
||||
; PPC64-NEXT: and r8, r8, r6
|
||||
; PPC64-NEXT: or r8, r8, r9
|
||||
; PPC64-NEXT: stwcx. r8, 0, r5
|
||||
; PPC64-NEXT: bne cr0, .LBB13_1
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: srw r3, r7, r3
|
||||
; PPC64-NEXT: lwsync
|
||||
; PPC64-NEXT: blr
|
||||
%val = atomicrmw xor i16* %mem, i16 %operand seq_cst
|
||||
; CHECK: lwsync
|
||||
ret i16 %val
|
||||
}
|
||||
define i32 @xchg_i32_acq_rel(i32* %mem, i32 %operand) {
|
||||
; CHECK-LABEL: xchg_i32_acq_rel
|
||||
; CHECK: lwsync
|
||||
; CHECK-LABEL: xchg_i32_acq_rel:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lwsync
|
||||
; CHECK-NEXT: .LBB14_1:
|
||||
; CHECK-NEXT: lwarx r5, 0, r3
|
||||
; CHECK-NEXT: stwcx. r4, 0, r3
|
||||
; CHECK-NEXT: bne cr0, .LBB14_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: mr r3, r5
|
||||
; CHECK-NEXT: lwsync
|
||||
; CHECK-NEXT: blr
|
||||
%val = atomicrmw xchg i32* %mem, i32 %operand acq_rel
|
||||
; CHECK: lwsync
|
||||
ret i32 %val
|
||||
}
|
||||
define i64 @and_i64_release(i64* %mem, i64 %operand) {
|
||||
; CHECK-LABEL: and_i64_release
|
||||
; CHECK: lwsync
|
||||
; PPC32-LABEL: and_i64_release:
|
||||
; PPC32: # %bb.0:
|
||||
; PPC32-NEXT: mflr r0
|
||||
; PPC32-NEXT: stw r0, 4(r1)
|
||||
; PPC32-NEXT: stwu r1, -16(r1)
|
||||
; PPC32-NEXT: .cfi_def_cfa_offset 16
|
||||
; PPC32-NEXT: .cfi_offset lr, 4
|
||||
; PPC32-NEXT: li r7, 3
|
||||
; PPC32-NEXT: bl __atomic_fetch_and_8
|
||||
; PPC32-NEXT: lwz r0, 20(r1)
|
||||
; PPC32-NEXT: addi r1, r1, 16
|
||||
; PPC32-NEXT: mtlr r0
|
||||
; PPC32-NEXT: blr
|
||||
;
|
||||
; PPC64-LABEL: and_i64_release:
|
||||
; PPC64: # %bb.0:
|
||||
; PPC64-NEXT: lwsync
|
||||
; PPC64-NEXT: .LBB15_1:
|
||||
; PPC64-NEXT: ldarx r5, 0, r3
|
||||
; PPC64-NEXT: and r6, r4, r5
|
||||
; PPC64-NEXT: stdcx. r6, 0, r3
|
||||
; PPC64-NEXT: bne cr0, .LBB15_1
|
||||
; PPC64-NEXT: # %bb.2:
|
||||
; PPC64-NEXT: mr r3, r5
|
||||
; PPC64-NEXT: blr
|
||||
%val = atomicrmw and i64* %mem, i64 %operand release
|
||||
; CHECK-NOT: [sync ]
|
||||
ret i64 %val
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user