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[AArch64] Fold more spilled/refilled COPYs.
Summary: Make AArch64InstrInfo::foldMemoryOperandImpl more general by folding all full COPYs between register classes of the same size that are either spilled or refilled. Reviewers: MatzeB, qcolombet Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27271 llvm-svn: 288439
This commit is contained in:
Geoff Berry
parent
078794f61e
commit
993081c749
@ -2598,8 +2598,8 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
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}
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}
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// Handle the case where a WZR/XZR copy is being spilled but the destination
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// register class doesn't contain WZR/XZR. For example:
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// Handle the case where a copy is being spilled or refilled but the source
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// and destination register class don't match. For example:
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//
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// %vreg0<def> = COPY %XZR; GPR64common:%vreg0
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//
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@ -2608,17 +2608,43 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
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//
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// STRXui %XZR, <fi#0>
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//
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if (MI.isFullCopy() && Ops.size() == 1 && Ops[0] == 0) {
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// This also eliminates spilled cross register class COPYs (e.g. between x and
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// d regs) of the same size. For example:
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//
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// %vreg0<def> = COPY %vreg1; GPR64:%vreg0, FPR64:%vreg1
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//
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// will be refilled as
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//
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// LDRDui %vreg0, fi<#0>
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//
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// instead of
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//
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// LDRXui %vregTemp, fi<#0>
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// %vreg0 = FMOV %vregTemp
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//
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if (MI.isFullCopy() && Ops.size() == 1 &&
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// Make sure we're only folding the explicit COPY defs/uses.
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(Ops[0] == 0 || Ops[0] == 1)) {
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineBasicBlock &MBB = *MI.getParent();
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const MachineOperand &DstMO = MI.getOperand(0);
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const MachineOperand &SrcMO = MI.getOperand(1);
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unsigned DstReg = DstMO.getReg();
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unsigned SrcReg = SrcMO.getReg();
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if (SrcReg == AArch64::WZR || SrcReg == AArch64::XZR) {
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const TargetRegisterInfo &TRI = getRegisterInfo();
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const TargetRegisterClass &RC = SrcReg == AArch64::WZR
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? AArch64::GPR32RegClass
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: AArch64::GPR64RegClass;
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storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
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&RC, &TRI);
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auto getRegClass = [&](unsigned Reg) {
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return TargetRegisterInfo::isVirtualRegister(Reg)
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? MRI.getRegClass(Reg)
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: TRI.getMinimalPhysRegClass(Reg);
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};
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const TargetRegisterClass &DstRC = *getRegClass(DstReg);
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const TargetRegisterClass &SrcRC = *getRegClass(SrcReg);
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if (DstRC.getSize() == SrcRC.getSize()) {
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if (Ops[0] == 0)
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storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
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&SrcRC, &TRI);
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else
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loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, &DstRC, &TRI);
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return &*--InsertPt;
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}
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}
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78
test/CodeGen/AArch64/spill-fold.ll
Normal file
78
test/CodeGen/AArch64/spill-fold.ll
Normal file
@ -0,0 +1,78 @@
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
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declare i32 @bar()
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declare i32 @baz()
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; Check that the spill of the zero value gets stored directly instead
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; of being copied from wzr and then stored.
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define i32 @test_zr_spill_fold1(i1 %c) {
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; CHECK-LABEL: test_zr_spill_fold1:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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ret i32 %x.0
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}
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; Similar to test_zr_spill_fold1, but with mis-matched register
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; class between %x.0 and the 0 from %if.then.
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define i32 @test_zr_spill_fold2(i1 %c) {
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; CHECK-LABEL: test_zr_spill_fold2:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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%x.1 = add i32 %x.0, 1
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ret i32 %x.1
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}
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; Similar to test_zr_spill_fold1, but with a cross register-class copy feeding a spill store.
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define float @test_cross_spill_fold(i32 %v) {
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; CHECK-LABEL: test_cross_spill_fold:
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entry:
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; CHECK: str w0, [sp, #[[SLOT:[0-9]+]]]
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%v.f = bitcast i32 %v to float
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
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; CHECK: ldr s0, [sp, #[[SLOT]]]
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ret float %v.f
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}
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; Similar to test_cross_spill_fold, but with a cross register-class copy fed by a refill load.
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define float @test_cross_spill_fold2(i32 %v) {
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; CHECK-LABEL: test_cross_spill_fold2:
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entry:
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; CHECK: str w0, [sp, #[[SLOT:[0-9]+]]]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
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; CHECK: ldr s0, [sp, #[[SLOT]]]
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%v.f = bitcast i32 %v to float
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ret float %v.f
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}
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@ -28,57 +28,3 @@ define void @test_sp(i32 %val) {
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ret void
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; CHECK: ret
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}
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declare i32 @bar()
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declare i32 @baz()
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; Check that the spill of the zero value gets stored directly instead
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; of being copied from wzr and then stored.
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define i32 @test_zr_spill_copyprop1(i1 %c) {
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; CHECK-LABEL: test_zr_spill_copyprop1:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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ret i32 %x.0
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}
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; Similar to test_zr_spill_copyprop1, but with mis-matched register
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; class between %x.0 and the 0 from %if.then.
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define i32 @test_zr_spill_copyprop2(i1 %c) {
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; CHECK-LABEL: test_zr_spill_copyprop2:
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entry:
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br i1 %c, label %if.else, label %if.then
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if.else:
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; CHECK: bl bar
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; CHECK-NEXT: str w0, [sp, #[[SLOT:[0-9]+]]]
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%call1 = tail call i32 @bar()
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br label %if.end
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if.then:
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; CHECK: bl baz
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; CHECK-NEXT: str wzr, [sp, #[[SLOT]]]
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%call2 = tail call i32 @baz()
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br label %if.end
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if.end:
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%x.0 = phi i32 [ 0, %if.then ], [ %call1, %if.else ]
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call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp}"() nounwind
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%x.1 = add i32 %x.0, 1
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ret i32 %x.1
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}
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