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Encode the register list operands for ARM mode LDM/STM instructions.

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llvm-svn: 117753
This commit is contained in:
Jim Grosbach 2010-10-30 00:37:59 +00:00
parent b68e0d0ee3
commit 996d1280bd
4 changed files with 23 additions and 0 deletions
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3
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -197,6 +197,9 @@ namespace {
unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
const { return 0; } const { return 0; }
unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
/// machine operand requires relocation, record the relocation and return /// machine operand requires relocation, record the relocation and return
/// zero. /// zero.

4
lib/Target/ARM/ARMInstrFormats.td
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@ -937,17 +937,21 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> { asm, cstr, pattern> {
bits<16> dsts;
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
let Inst{15-0} = dsts;
} }
class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
asm, cstr, pattern> { asm, cstr, pattern> {
bits<16> srcs;
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{22} = 0; // S bit let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
let Inst{15-0} = srcs;
} }
// Unsigned multiply, multiply-accumulate instructions. // Unsigned multiply, multiply-accumulate instructions.

1
lib/Target/ARM/ARMInstrInfo.td
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@ -279,6 +279,7 @@ def brtarget : Operand<OtherVT>;
// A list of registers separated by comma. Used by load/store multiple. // A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> { def reglist : Operand<i32> {
string EncoderMethod = "getRegisterListOpValue";
let PrintMethod = "printRegisterList"; let PrintMethod = "printRegisterList";
} }

15
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -98,6 +98,9 @@ public:
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const; unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
unsigned getNumFixupKinds() const { unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
return 0; return 0;
@ -285,6 +288,18 @@ unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
return lsb | (msb << 5); return lsb | (msb << 5);
} }
unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
unsigned Op) const {
// Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
// register in the list, set the corresponding bit.
unsigned Binary = 0;
for (unsigned i = Op; i < MI.getNumOperands(); ++i) {
unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
Binary |= 1 << regno;
}
return Binary;
}
void ARMMCCodeEmitter:: void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS, EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {