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Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350

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llvm-svn: 40518
This commit is contained in:
Christopher Lamb 2007-07-26 07:48:21 +00:00
parent 413d222576
commit 9a0d88efde
6 changed files with 72 additions and 7 deletions
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4
include/llvm/Target/TargetInstrInfo.h
View File

@ -177,7 +177,9 @@ public:
enum {
PHI = 0,
INLINEASM = 1,
LABEL = 2
LABEL = 2,
EXTRACT_SUBREG = 3,
INSERT_SUBREG = 4
};
unsigned getNumOpcodes() const { return NumOpcodes; }

12
lib/Target/Target.td
View File

@ -321,6 +321,18 @@ def LABEL : Instruction {
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
def EXTRACT_SUBREG : Instruction {
let OutOperandList = (ops variable_ops);
let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
def INSERT_SUBREG : Instruction {
let OutOperandList = (ops variable_ops);
let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize

12
utils/TableGen/CodeEmitterGen.cpp
View File

@ -26,7 +26,9 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
Record *R = *I;
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
R->getName() == "LABEL") continue;
R->getName() == "LABEL" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@ -97,7 +99,9 @@ void CodeEmitterGen::run(std::ostream &o) {
if (R->getName() == "PHI" ||
R->getName() == "INLINEASM" ||
R->getName() == "LABEL") {
R->getName() == "LABEL" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG") {
o << " 0U";
continue;
}
@ -127,7 +131,9 @@ void CodeEmitterGen::run(std::ostream &o) {
if (InstName == "PHI" ||
InstName == "INLINEASM" ||
InstName == "LABEL") continue;
InstName == "LABEL"||
InstName == "EXTRACT_SUBREG" ||
InstName == "INSERT_SUBREG") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();

16
utils/TableGen/CodeGenTarget.cpp
View File

@ -275,14 +275,28 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
if (I == Instructions.end()) throw "Could not find 'LABEL' instruction!";
const CodeGenInstruction *LABEL = &I->second;
I = getInstructions().find("EXTRACT_SUBREG");
if (I == Instructions.end())
throw "Could not find 'EXTRACT_SUBREG' instruction!";
const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
I = getInstructions().find("INSERT_SUBREG");
if (I == Instructions.end())
throw "Could not find 'INSERT_SUBREG' instruction!";
const CodeGenInstruction *INSERT_SUBREG = &I->second;
// Print out the rest of the instructions now.
NumberedInstructions.push_back(PHI);
NumberedInstructions.push_back(INLINEASM);
NumberedInstructions.push_back(LABEL);
NumberedInstructions.push_back(EXTRACT_SUBREG);
NumberedInstructions.push_back(INSERT_SUBREG);
for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
if (&II->second != PHI &&
&II->second != INLINEASM &&
&II->second != LABEL)
&II->second != LABEL &&
&II->second != EXTRACT_SUBREG &&
&II->second != INSERT_SUBREG)
NumberedInstructions.push_back(&II->second);
}

31
utils/TableGen/DAGISelEmitter.cpp
View File

@ -3729,6 +3729,33 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " MVT::Other, Tmp, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_EXTRACT_SUBREG(const SDOperand &N) {\n"
<< " SDOperand N0 = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N0, Tmp);\n"
<< "}\n\n";
OS << "SDNode *Select_INSERT_SUBREG(const SDOperand &N) {\n"
<< " SDOperand N0 = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
<< " SDOperand N2 = N.getOperand(2);\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getValue();\n"
<< " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " AddToISelQueue(N1);\n"
<< " if (N0.getOpcode() == ISD::UNDEF) {\n"
<< " return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N1, Tmp);\n"
<< " } else {\n"
<< " AddToISelQueue(N0);\n"
<< " return CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N0, N1, Tmp);\n"
<< " }\n"
<< "}\n\n";
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDOperand N) {\n"
<< " if (N.getOpcode() >= ISD::BUILTIN_OP_END &&\n"
@ -3766,7 +3793,9 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " return NULL;\n"
<< " }\n"
<< " case ISD::INLINEASM: return Select_INLINEASM(N);\n"
<< " case ISD::LABEL: return Select_LABEL(N);\n";
<< " case ISD::LABEL: return Select_LABEL(N);\n"
<< " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
<< " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n";
// Loop over all of the case statements, emiting a call to each method we

4
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -325,7 +325,9 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
// This isn't an error if this is a builtin instruction.
if (R->getName() != "PHI" &&
R->getName() != "INLINEASM" &&
R->getName() != "LABEL")
R->getName() != "LABEL" &&
R->getName() != "EXTRACT_SUBREG" &&
R->getName() != "INSERT_SUBREG")
throw R->getName() + " doesn't have a field named '" +
Val->getValue() + "'!";
return;