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Don't build tail calls to functions with three inreg arguments on x86-32 PIC.
Fixes PR15250! llvm-svn: 175092
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@ -2814,7 +2814,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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SelectionDAG &DAG) const {
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if (!IsTailCallConvention(CalleeCC) &&
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CalleeCC != CallingConv::C)
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return false;
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@ -2853,7 +2853,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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// An stdcall caller is expected to clean up its arguments; the callee
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// isn't going to do that.
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if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
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if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
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return false;
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// Do not sibcall optimize vararg calls unless all arguments are passed via
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@ -2973,9 +2973,15 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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// callee-saved registers are restored. These happen to be the same
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// registers used to pass 'inreg' arguments so watch out for those.
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if (!Subtarget->is64Bit() &&
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!isa<GlobalAddressSDNode>(Callee) &&
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!isa<ExternalSymbolSDNode>(Callee)) {
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((!isa<GlobalAddressSDNode>(Callee) &&
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!isa<ExternalSymbolSDNode>(Callee)) ||
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getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
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unsigned NumInRegs = 0;
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// In PIC we need an extra register to formulate the address computation
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// for the callee.
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unsigned MaxInRegs =
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(getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (!VA.isRegLoc())
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@ -2984,7 +2990,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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switch (Reg) {
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default: break;
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case X86::EAX: case X86::EDX: case X86::ECX:
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if (++NumInRegs == 3)
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if (++NumInRegs == MaxInRegs)
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return false;
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break;
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}
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