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[AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vector
If we have a 64-bit EXT where one of the operands is a subvector of a 128-bit vector then in some cases we can eliminate an extract_subvector by converting to a 128-bit EXT of the 128-bit vector. Differential Revision: https://reviews.llvm.org/D53582 llvm-svn: 345275
This commit is contained in:
John Brawn
parent
e4b39c84d1
commit
9a9d09f98c
@ -4185,6 +4185,9 @@ def : Pat<(concat_vectors (v2i32 V64:$Rd),
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defm EXT : SIMDBitwiseExtract<"ext">;
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def AdjustExtImm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(8 + N->getZExtValue(), SDLoc(N), MVT::i32);
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}]>;
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multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
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def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
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(EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
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@ -4194,6 +4197,22 @@ multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
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// 128-bit vector.
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def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),
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(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
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// A 64-bit EXT of two halves of the same 128-bit register can be done as a
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// single 128-bit EXT.
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def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)),
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(extract_subvector V128:$Rn, (i64 N)),
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(i32 imm:$imm))),
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(EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, imm:$imm), dsub)>;
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// A 64-bit EXT of the high half of a 128-bit register can be done using a
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// 128-bit EXT of the whole register with an adjustment to the immediate. The
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// top half of the other operand will be unset, but that doesn't matter as it
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// will not be used.
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def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 N)),
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V64:$Rm,
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(i32 imm:$imm))),
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(EXTRACT_SUBREG (EXTv16i8 V128:$Rn,
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(SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
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(AdjustExtImm imm:$imm)), dsub)>;
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}
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defm : ExtPat<v8i8, v16i8, 8>;
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345
test/CodeGen/AArch64/ext-narrow-index.ll
Normal file
345
test/CodeGen/AArch64/ext-narrow-index.ll
Normal file
@ -0,0 +1,345 @@
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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; Tests of shufflevector where the index operand is half the width of the vector
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; operands. We should get one ext instruction and not two.
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; i8 tests
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define <8 x i8> @i8_off0(<16 x i8> %arg1, <16 x i8> %arg2) {
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; CHECK-LABEL: i8_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_off1(<16 x i8> %arg1, <16 x i8> %arg2) {
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; CHECK-LABEL: i8_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #1
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_off8(<16 x i8> %arg1, <16 x i8> %arg2) {
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; CHECK-LABEL: i8_off8:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_off15(<16 x i8> %arg1, <16 x i8> %arg2) {
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; CHECK-LABEL: i8_off15:
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; CHECK: ext v0.16b, v0.16b, v1.16b, #15
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_off22(<16 x i8> %arg1, <16 x i8> %arg2) {
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; CHECK-LABEL: i8_off22:
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; CHECK: ext v0.16b, v1.16b, v1.16b, #6
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29>
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ret <8 x i8> %shuffle
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}
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; i16 tests
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define <4 x i16> @i16_off0(<8 x i16> %arg1, <8 x i16> %arg2) {
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; CHECK-LABEL: i16_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_off1(<8 x i16> %arg1, <8 x i16> %arg2) {
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; CHECK-LABEL: i16_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #2
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> %arg2, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_off7(<8 x i16> %arg1, <8 x i16> %arg2) {
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; CHECK-LABEL: i16_off7:
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; CHECK: ext v0.16b, v0.16b, v1.16b, #14
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> %arg2, <4 x i32> <i32 7, i32 8, i32 9, i32 10>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_off8(<8 x i16> %arg1, <8 x i16> %arg2) {
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; CHECK-LABEL: i16_off8:
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; CHECK: mov v0.16b, v1.16b
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> %arg2, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
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ret <4 x i16> %shuffle
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}
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; i32 tests
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define <2 x i32> @i32_off0(<4 x i32> %arg1, <4 x i32> %arg2) {
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; CHECK-LABEL: i32_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> %arg2, <2 x i32> <i32 0, i32 1>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_off1(<4 x i32> %arg1, <4 x i32> %arg2) {
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; CHECK-LABEL: i32_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #4
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> %arg2, <2 x i32> <i32 1, i32 2>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_off3(<4 x i32> %arg1, <4 x i32> %arg2) {
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; CHECK-LABEL: i32_off3:
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; CHECK: ext v0.16b, v0.16b, v1.16b, #12
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> %arg2, <2 x i32> <i32 3, i32 4>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_off4(<4 x i32> %arg1, <4 x i32> %arg2) {
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; CHECK-LABEL: i32_off4:
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; CHECK: mov v0.16b, v1.16b
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> %arg2, <2 x i32> <i32 4, i32 5>
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ret <2 x i32> %shuffle
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}
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; i64 tests
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define <1 x i64> @i64_off0(<2 x i64> %arg1, <2 x i64> %arg2) {
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; CHECK-LABEL: i64_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> %arg2, <1 x i32> <i32 0>
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ret <1 x i64> %shuffle
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}
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define <1 x i64> @i64_off1(<2 x i64> %arg1, <2 x i64> %arg2) {
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; CHECK-LABEL: i64_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> %arg2, <1 x i32> <i32 1>
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ret <1 x i64> %shuffle
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}
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define <1 x i64> @i64_off2(<2 x i64> %arg1, <2 x i64> %arg2) {
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; CHECK-LABEL: i64_off2:
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; CHECK: mov v0.16b, v1.16b
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> %arg2, <1 x i32> <i32 2>
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ret <1 x i64> %shuffle
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}
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; i8 tests with second operand zero
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define <8 x i8> @i8_zero_off0(<16 x i8> %arg1) {
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; CHECK-LABEL: i8_zero_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_zero_off1(<16 x i8> %arg1) {
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; CHECK-LABEL: i8_zero_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #1
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_zero_off8(<16 x i8> %arg1) {
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; CHECK-LABEL: i8_zero_off8:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_zero_off15(<16 x i8> %arg1) {
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; CHECK-LABEL: i8_zero_off15:
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; CHECK: movi [[REG:v[0-9]+]].2d, #0
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; CHECK: ext v0.16b, v0.16b, [[REG]].16b, #15
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22>
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ret <8 x i8> %shuffle
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}
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define <8 x i8> @i8_zero_off22(<16 x i8> %arg1) {
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; CHECK-LABEL: i8_zero_off22:
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; CHECK: movi v0.2d, #0
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29>
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ret <8 x i8> %shuffle
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}
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; i16 tests with second operand zero
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define <4 x i16> @i16_zero_off0(<8 x i16> %arg1) {
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; CHECK-LABEL: i16_zero_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_zero_off1(<8 x i16> %arg1) {
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; CHECK-LABEL: i16_zero_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #2
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_zero_off7(<8 x i16> %arg1) {
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; CHECK-LABEL: i16_zero_off7:
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; CHECK: movi [[REG:v[0-9]+]].2d, #0
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; CHECK: ext v0.16b, v0.16b, [[REG]].16b, #14
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 7, i32 8, i32 9, i32 10>
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ret <4 x i16> %shuffle
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}
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define <4 x i16> @i16_zero_off8(<8 x i16> %arg1) {
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; CHECK-LABEL: i16_zero_off8:
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; CHECK: movi v0.2d, #0
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
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ret <4 x i16> %shuffle
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}
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; i32 tests with second operand zero
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define <2 x i32> @i32_zero_off0(<4 x i32> %arg1) {
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; CHECK-LABEL: i32_zero_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 0, i32 1>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_zero_off1(<4 x i32> %arg1) {
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; CHECK-LABEL: i32_zero_off1:
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; CHECK-NOT: mov
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; CHECK: ext v0.16b, v0.16b, v0.16b, #4
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 1, i32 2>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_zero_off3(<4 x i32> %arg1) {
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; CHECK-LABEL: i32_zero_off3:
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; CHECK: movi [[REG:v[0-9]+]].2d, #0
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; CHECK: ext v0.16b, v0.16b, [[REG]].16b, #12
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 3, i32 4>
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ret <2 x i32> %shuffle
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}
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define <2 x i32> @i32_zero_off4(<4 x i32> %arg1) {
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; CHECK-LABEL: i32_zero_off4:
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; CHECK: movi v0.2d, #0
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5>
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ret <2 x i32> %shuffle
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}
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; i64 tests with second operand zero
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define <1 x i64> @i64_zero_off0(<2 x i64> %arg1) {
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; CHECK-LABEL: i64_zero_off0:
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; CHECK-NOT: mov
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; CHECK-NOT: ext
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; CHECK: ret
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entry:
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%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> zeroinitializer, <1 x i32> <i32 0>
|
||||
ret <1 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <1 x i64> @i64_zero_off1(<2 x i64> %arg1) {
|
||||
; CHECK-LABEL: i64_zero_off1:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-NOT: ext
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
|
||||
ret <1 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <1 x i64> @i64_zero_off2(<2 x i64> %arg1) {
|
||||
; CHECK-LABEL: i64_zero_off2:
|
||||
; CHECK: fmov d0, xzr
|
||||
; CHECK-NOT: ext
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle = shufflevector <2 x i64> %arg1, <2 x i64> zeroinitializer, <1 x i32> <i32 2>
|
||||
ret <1 x i64> %shuffle
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user