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Rewrite the section on trap values to contain a generic description
of dependence and define trap values in terms of dependence, instead of trying to cover the concept with a flurry of ad-hoc rules. The dependence model isn't complete yet, but it's already much more rigorous than the description it replaces. llvm-svn: 102479
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@ -2336,80 +2336,104 @@ has undefined behavior.</p>
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effects has nevertheless detected a condition which results in undefined
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behavior.</p>
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<p>Any value other than a non-intrinsic call, invoke, or phi with a trap
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operand has trap as its result value. Any instruction with
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a trap operand which may have side effects emits those side effects as
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if it had an undef operand instead. If the side effects are externally
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visible, the behavior is undefined.</p>
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<p>There is currently no way of representing a trap value in the IR; they
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only exist when produced by instructions such as
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<a href="#i_add"><tt>add</tt></a> with the <tt>nsw</tt> flag.</p>
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<p>Trap values may be stored to memory; a load from memory including any
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part of a trap value results in a (full) trap value.</p>
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<p>For example:</p>
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<p>Trap value behavior is defined in terms of value <i>dependence</i>:</p>
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<!-- FIXME: In the case of multiple threads, this only applies to loads from
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the same thread as the store, or loads which are sequenced after the
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<p>
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<ul>
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<li>Values other than <a href="#i_phi"><tt>phi</tt></a> nodes depend on
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their operands.</li>
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<li><a href="#i_phi"><tt>Phi</tt></a> nodes depend on the operand corresponding
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to their dynamic predecessor basic block.</li>
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<li>Function arguments depend on the corresponding actual argument values in
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the dynamic callers of their functions.</li>
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<li><a href="#i_call"><tt>Call</tt></a> instructions depend on the
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<a href="#i_ret"><tt>ret</tt></a> instructions that dynamically transfer
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control back to them.</li>
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<li>Non-volatile loads and stores depend on the most recent stores to all of the
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referenced memory addresses, following the order in the IR
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(including loads and stores implied by intrinsics such as
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<a href="#int_memcpy"><tt>@llvm.memcpy</tt></a>.)</li>
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<!-- FIXME: padding in the middle of a struct -->
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<!-- TODO: In the case of multiple threads, this only applies to loads and
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stores from the same thread as the store, or which are sequenced after the
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store by synchronization. -->
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<div class="doc_code">
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<pre>
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%trap = sub nuw i32 0, 1 ; Results in a trap value.
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%still_trap = and i32 %trap, 0 ; Whereas (and i32 undef, 0) would return 0.
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%trap_yet_again = getelementptr i32* @h, i32 %still_trap
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store i32 0, i32* %trap_yet_again ; undefined behavior
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<!-- TODO: floating-point exception state -->
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volatile store i32 %trap, i32* @g ; External observation; undefined behavior.
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%trap2 = load i32* @g ; Returns a trap value, not just undef.
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%narrowaddr = bitcast i32* @g to i16*
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%wideaddr = bitcast i32* @g to i64*
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%trap3 = load 16* %narrowaddr ; Returns a trap value
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%trap4 = load i64* %widaddr ; Returns a trap value, not partial trap.
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</pre>
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</div>
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<li>An instruction with externally visible side effects depends on the most
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recent preceding instruction with externally visible side effects, following
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the order in the IR. (This includes volatile loads and stores.)</li>
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<p>If a <a href="#i_br"><tt>br</tt></a> or
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<a href="#i_switch"><tt>switch</tt></a> instruction has a trap value
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operand, all non-phi non-void instructions which control-depend on it
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have trap as their result value. A <a href="#i_phi"><tt>phi</tt></a>
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node with an incoming value associated with a control edge which is
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control-dependent on it has trap as its result value when control is
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transferred from that block. If any instruction which control-depends
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on the <tt>br</tt> or <tt>switch</tt> invokes externally visible side
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effects, the behavior of the program is undefined. For example:</p>
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<li>An instruction <i>control-depends</i> on a <a href="#i_br"><tt>br</tt></a>,
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<a href="#i_switch"><tt>switch</tt></a>, or
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<a href="#i_indirectbr"><tt>indirectbr</tt></a> if the <tt>br</tt>,
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<tt>switch</tt>, or <tt>indirectbr</tt> has multiple successors and the
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instruction is always executed when control transfers to one of the
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successors, and may not be executed when control is transfered to
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another.</li>
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<!-- FIXME: What about exceptions thrown from control-dependent instrs? -->
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<!-- FIXME: invoke, unwind, exceptions -->
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<li>Dependence is transitive.</li>
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</ul>
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</p>
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<p>Whenever a trap value is generated, all values which depend on it evaluate
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to trap. If they have side effects, the evoke their side effects as if each
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operand with a trap value were undef. If they have externally-visible side
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effects, the behavior is undefined.</p>
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<p>Here are some examples:</p>
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<div class="doc_code">
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<pre>
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entry:
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%trap = sub nuw i32 0, 1 ; Results in a trap value.
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%cmp = icmp i32 slt %trap, 0 ; Still trap.
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%still_trap = and i32 %trap, 0 ; Whereas (and i32 undef, 0) would return 0.
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%trap_yet_again = getelementptr i32* @h, i32 %still_trap
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store i32 0, i32* %trap_yet_again ; undefined behavior
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store i32 %trap, i32* @g ; Trap value conceptually stored to memory.
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%trap2 = load i32* @g ; Returns a trap value, not just undef.
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volatile store i32 %trap, i32* @g ; External observation; undefined behavior.
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%narrowaddr = bitcast i32* @g to i16*
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%wideaddr = bitcast i32* @g to i64*
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%trap3 = load 16* %narrowaddr ; Returns a trap value.
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%trap4 = load i64* %widaddr ; Returns a trap value.
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%cmp = icmp i32 slt %trap, 0 ; Returns a trap value.
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%br i1 %cmp, %true, %end ; Branch to either destination.
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true:
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volatile store i32 0, i32* @g ; Externally visible side effects
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; control-dependent on %cmp.
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; Undefined behavior.
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volatile store i32 0, i32* @g ; This is control-dependent on %cmp, so
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; it has undefined behavior.
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br label %end
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end:
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%p = phi i32 [ 0, %entry ], [ 1, %true ]
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; Both edges into this PHI are
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; control-dependent on %cmp, so this
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; results in a trap value.
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; always results in a trap value.
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volatile store i32 0, i32* @g ; %end is control-equivalent to %entry
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; so this is defined (ignoring earlier
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; undefined behavior in this example).
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</pre>
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</div>
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<p>There is currently no way of representing a trap constant in the IR; they
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only exist when produced by certain instructions, such as an
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<a href="#i_add"><tt>add</tt></a> with the <tt>nsw</tt> flag
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set, when overflow occurs.</p>
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</div>
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<!-- ======================================================================= -->
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